ADIN1100BCPZ-R7 datasheet(2/80 Pages) AD

2 / 80 page

Data Sheet

ADIN1100

TABLE OF CONTENTS

analog.com

Rev. B | 2 of 80

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................1

Specifications........................................................ 4

Timing Characteristics........................................... 7

Power-Up Timing................................................7

Management Interface Timing ...........................7

Absolute Maximum Ratings...................................8

Thermal Resistance........................................... 8

Electrostatic Discharge (ESD) Ratings...............8

ESD Caution.......................................................8

Pin Configuration and Function Descriptions........ 9

Typical Performance Characteristics................... 12

Theory of Operation.............................................13

Power Supply Domains.................................... 13

MAC Interface.................................................. 13

Transmit Amplitude Configuration.................... 14

Master/Slave Configuration.............................. 14

Autonegotiation................................................ 15

Management Interface..................................... 18

Reset Operations............................................. 19

Status LEDs..................................................... 20

Link Status Pin................................................. 22

Power-Down Modes......................................... 22

Hardware Configuration Pins...............................23

Overview.......................................................... 23

Unmanaged Applications................................. 23

Managed Applications......................................23

Hardware Configuration Pins Functions...........23

Bringing Up 10BASE-T1L Links.......................... 26

Unmanaged PHY Operation.............................26

Managed PHY Operation................................. 26

On-Chip Diagnostics............................................29

Loopback Modes..............................................29

Frame Generator and Checker........................ 30

Frame Generator and Checker Link Test......... 30

Test Modes.......................................................32

Time Domain Reflectometry (TDR).................. 32

Applications Information...................................... 34

System Level Power Management...................34

LED Circuit Examples...................................... 34

Component Recommendations........................35

Electromagnetic Compatibility (EMC) and

Electromagnetic Immunity (EMI) ................... 37

MDIO Interface.................................................... 38

Clause 22......................................................... 38

Clause 45......................................................... 39

Recommended Register Operation..................40

Ethernet Clause 22 Register Details................ 41

Ethernet Clause 45 Register Details................ 43

PCB Layout Recommendations.......................... 79

Land Pattern.....................................................79

Component Placement and Routing................ 79

Crystal Placement and Routing........................79

PCB Stack........................................................79

Outline Dimensions............................................. 80

Ordering Guide.................................................80

Evaluation Boards............................................ 80

REVISION HISTORY

8/2023—Rev. A to Rev. B

Changes to General Description Section.........................................................................................................1

1/2023—Rev. 0 to Rev. A

Changes to Features Section ......................................................................................................................... 1

Changes to Clock Input Voltage Range Parameter; Table 1 ...........................................................................4

Changes to Table 2..........................................................................................................................................5

Changes to Single-Supply Applications Section............................................................................................ 13

Changes to Long Reach and Trunk/Spur Applications Section..................................................................... 13

Changes to High Voltage Transmit Level Request Advertisement Section .................................................. 15

Changes to Determination of Transmit Level Resolution Section .................................................................16

Change to Table 11........................................................................................................................................ 16

Changes to Master/Slave Advertisement Section..........................................................................................17

Changes to Forced Master/Slave Configuration Advertisement Section....................................................... 17

Changes to Determination of Master/Slave Configuration Section................................................................17

Changes to Autonegotiation Fail Section.......................................................................................................18

ADIN1100BCPZ-R7 数据表(PDF) 2 Page - Analog Devices

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