ADIN1100BCPZ-R7 datasheet(13/80 Pages) AD

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Data Sheet

ADIN1100

THEORY OF OPERATION

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Rev. B | 13 of 80

The ADIN1100 is a low power, single port 10BASE-T1L Ethernet

PHY device, compliant with the IEEE 802.3cg Ethernet standard for

long reach, 10 Mbps single pair Ethernet.

The ADIN1100 integrates the following features:

►

PHY core with common analog circuitry

►

Input and output clock buffering

►

MDIO interface to control subsystem registers, clock, and soft-

ware resets

►

MAC interface control logic

►

Hardware configuration pins

►

Configurable hardware interrupt pin

►

Two configurable LED pins

POWER SUPPLY DOMAINS

The ADIN1100 has four power supply domains and requires a

minimum of one supply rail.

►

AVDD_H is the analog power supply input for the analog front

end (AFE) circuitry in the ADIN1100.

►

AVDD_L is the analog supply voltage for the internal LDO cir-

cuits. AVDD_L can be connected to the AVDD_H rail in single

supply mode, or to an alternative lower voltage rail in dual

supplies mode for lower power consumption.

►

DVDD_1P1 is the 1.1 V digital core power supply input. It can

operate from the internal 1.1 V LDO output available on the

DLDO_1P1 pin. Alternatively, DVDD_1P1 can be driven from an

external 1.1 V supply for lower power consumption.

►

VDDIO is the digital power supply input for the ADIN1100 MAC

interface, MDIO, and digital inputs/outputs (I/Os). It can be con-

nected directly to the AVDD_L rail or to an external power rail.

The System Level Power Management section describes various

application circuits that can be used as reference.

Single-Supply Applications

In a single-supply application, connect AVDD_H and AVDD_L to

VDDIO, and in the ADIN1100, use the internal 1.1 V LDO circuit for

DVDD_1P1. The appropriate supply voltage used depends on the

end application and cable length. A recommended circuit is shown

in the Single-Supply Configuration section.

Long Reach and Trunk/Spur Applications

The 1.0 V p-p transmit operating mode supports the spur use case

and can operate at a lower AVDD_H supply voltage of 1.8 V. The

ADIN1100 in this mode supports intrinsic safety applications.

The higher transmit operating mode of 2.4 V p-p supports trunk

applications and requires a higher AVDD_H supply voltage of 3.3

V. This mode can be used for longer cable lengths in industrial

Ethernet environments with higher noise levels.

MAC INTERFACE

The ADIN1100 provides the option of MII, RMII, or RGMII MAC

interfaces. The MAC interface is selected using the hardware

configuration pins (RX_CLK/RXC/MACIF_SEL0 and RX_ER/MA-

CIF_SEL1) or via the management interface (MDIO). The two

hardware configuration pins for MAC interface selection strap the

ADIN1100 configuration after power-up, hardware reset, or software

reset.

By default (hardware configuration pins floating), the MAC interface

is configured in RMII mode. See the MAC Interface Selection for

more details on how to configure the MAC interface using the

hardware configuration pins.

It is recommended to use the hardware configuration pins for the

MAC interface selection because the supported interfaces have

different clock and pin mapping requirements.

MII Interface Mode

For the MII receive interface, the ADIN1100 generates a 2.5 MHz

reference clock on RX_CLK to synchronize the RXD_3 to RXD_0

receive data signals. RX_DV indicates to the MAC that valid data

is present on the RXD_3 to RXD_0 signals. RX_ER is driven high

by the ADIN1100 if an error was detected in the frame that was

received from the MDI interface and is being transmitted to the

MAC interface.

For the MII transmit interface, the ADIN1100 generates a 2.5 MHz

reference clock on TX_CLK. The MAC transmits data on TXD_3

to TXD_0 that is synchronized with TX_CLK. The MAC asserts

TX_EN high to indicate to the ADIN1100 that transmission data is

available on the TXD_3 to TXD_0 signal lines.

Figure 10. MII MAC PHY Interface Signals

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