ADIN1100BCPZ-R7 datasheet(10/80 Pages) AD

10 / 80 page

Data Sheet

ADIN1100

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. B | 10 of 80

Table 8. Pin Function Descriptions (Continued)

Pin No.

Mnemonic1

PU/PD2

Description

TXD_2

Reduced Gigabit Media Independent Interface (RGMII)/MII Transmit Data 2 Input.

See the MAC Interface section.

TXD_3/MEDIA_CNV

RGMII/MII Transmit Data 3 Input (TXD_3). See the MAC Interface section.

Media Converter Hardware Configuration Pin (MEDIA_CNV).

RXD_3/PHYAD_1

RGMII/MII Receive Data 3 Output (RXD_3). See the MAC Interface section.

PHY Address Hardware Configuration Pin 1 (PHYAD_1).

RXD_2/PHYAD_0

RGMII/MII Receive Data 2 Output (RXD_2). See the MAC Interface section.

PHY Address Hardware Configuration Pin 0 (PHYAD_0).

RXD_1/MS_SEL

RGMII/RMII/MII Receive Data 1 Output (RXD_1). See the MAC Interface section.

Master/Slave Selection (MS_SEL). Set high for prefer master selection and low for

prefer slave selection. See Table 18.

RXD_0/TX2P4_EN

RGMII/RMII/MII Receive Data 0 Output (RXD_0). See the MAC Interface section.

Transmit Level Amplitude Hardware Configuration Pin (TX2P4_EN). Set high for

1 V p-p transmit amplitude. A low supports both 1 V p-p and 2.4 V p-p transmit

amplitudes. See Table 19.

RX_CLK/RXC/MACIF_SEL0

2.5 MHz MII Receive Clock Output (RX_CLK).

2.5 MHz RGMII Receive Clock Output (RXC).

MAC Interface Selection Hardware Configuration Pin 0 (MACIF_SEL0). See the

MAC Interface Selection section.

RX_DV/RX_CTL/SWPD_EN

RMII/MII Mode Received Data Valid Output (RX_DV). This signal is known as

CRS_DV in RMII mode. When asserted high, RX_DV indicates that valid data is

present on the RXD_x lines.

RGMII Mode Receive Control Signal (RX_CTL). RX_CTL is a combination of the

RX_DV and RX_ER signals using both edges of RXC.

Software Power-Down Configuration (SWPD_EN). Set SWPD_EN low to configure

the PHY to enter software power-down mode after power-up or reset. See Table 17.

RX_ER/MACIF_SEL1

RMII/MII Mode Receive Error Detected Output (RX_ER). When asserted high,

RX_ER indicates that the PHY has detected a receive error.

MAC Interface Selection Hardware Configuration Pin 1 (MACIF_SEL1). See Table

21.

TX_ER

RMII/MII Mode Transmit Error Input Detection from the MAC to the PHY.

TX_EN/TX_CTL

RMII/MII Mode Transmit Enable Input from the MAC to the PHY (TX_EN). TX_EN

indicates that transmission data is available on the TXD_x lines.

RGMII Mode Transmit Control Signal (TX_CTL). TX_CTL is a combination of the

TX_EN and RX_ER signals using both edges of TXC.

TX_CLK/TXC

2.5 MHz MII Transmit Clock Output (TX_CLK).

2.5 MHz RGMII Transmit Clock Input (TXC).

TXD_0

RGMII/RMII/MII Transmit Data 0 Input. See the MAC Interface section.

TXD_1

RGMII/RMII/MII Transmit Data 1 Input. See the MAC Interface section.

Status

LED_0

General-Purpose, Programmable LED Indicator 0. The LED can be active high or

active low. By default, LED_0 is configured to turn on when a link is established

and blink when there is activity. See the Status LEDs section.

LINK_ST/PHYAD_2

Link Status Output (LINK_ST). LINK_ST indicates whether a valid link has been

established. LINK_ST is active high.

PHY Address Hardware Configuration Pin 2 (PHYAD_2).

LED_1

General-Purpose, Programmable LED Indicator 1. The LED can be active high or

active low. By default, LED_1 is disabled. See the Status LEDs section.

LDO and Reference Decoupling

ADIN1100BCPZ-R7 数据表(PDF) 10 Page - Analog Devices

ADIN1100BCPZ-R7 数据表(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载