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ADIN1100BCPZ-R7 数据表(PDF) 50 Page - Analog Devices |
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ADIN1100BCPZ-R7 数据表(HTML) 50 Page - Analog Devices |
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50 / 80 page  Data Sheet ADIN1100 REGISTER SUMMARY analog.com Rev. B | 50 of 80 Table 53. Bit Descriptions for PMA_PMD_BT1_ABILITY Bits Bit Name Description Reset Access [15:4] RESERVED Reserved. 0x0 R 3 B10S_ABILITY 10BASE-T1S Ability. This bit always reads as 0 because the PMA/PMD does not support 10BASE-T1S. 0x0 R 2 B10L_ABILITY 10BASE-T1L Ability. This bit always reads as 1 because the PMA/PMD supports 10BASE-T1L. 0x1 R 1 B1000_ABILITY 1000BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 1000BASE-T1. 0x0 R 0 B100_ABILITY 100BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 100BASE-T1. 0x0 R BASE-T1 PMA/PMD Control Register Device Address: 0x01; Register Address: 0x0834, Reset: 0x8002, Name: PMA_PMD_BT1_CONTROL This address corresponds to the BASE-T1 PMA/PMD control register specified in Clause 45.2.1.185 of Standard 802.3. Table 54. Bit Descriptions for PMA_PMD_BT1_CONTROL Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x1 R 14 CFG_MST Master and Slave Configuration. CFG_MST is used only when autonegotiation is disabled. Otherwise, this value is determined by the autonegotiation process itself. When this bit is set as 1, the device is configured as a master. Otherwise, the device is configured as a slave. Pin dependent R/W [13:4] RESERVED Reserved. 0x0 R [3:0] BT1_TYPE_SEL BASE-T1 Type Selection. See IEEE Standard 802.3 for the following control register bit definitions (where X means don't care): 0x2 R/W 1XXX: reserved. 01XX: reserved. 0011: 10BASE-T1S . 0010: 10BASE-T1L. 0001: 1000BASE-T. 0000: 100BASE-T. BT1_TYPE_SEL is used only when autonegotiation is disabled and forced link configuration mode is enabled. If autonegotiation is enabled, the PHY type is determined by the autonegotiation process itself. Note that for ADIN1100, the only valid value is for 10BASE-T1L. 0010: 10BASE-T1L. 10BASE-T1L PMA Control Register Device Address: 0x01; Register Address: 0x08F6, Reset: 0x0000, Name: B10L_PMA_CNTRL This address corresponds to the 10BASE-T1L PMA control register specified in Clause 45.2.1.186a of Standard 802.3cg. Table 55. Bit Descriptions for B10L_PMA_CNTRL Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R/W SC 14 B10L_TX_DIS_MODE_EN 10BASE-T1L Transmit Disable Mode. When this bit is set to 1, it disables output on the transmit path. Otherwise, it enables output on the transmit path. 0x0 R/W 13 RESERVED Reserved. 0x0 R 12 B10L_TX_LVL_HI 10BASE-T1L Transmit Voltage Amplitude Control. This configuration is only used when autonegotiation is disabled. Otherwise, the configuration is decided by the autonegotiation process. When this bit is set as 1, the device works in the 2.4 V p-p operating mode. Otherwise, the device works in the 1.0 V p-p operating mode. Pin dependent R/W 11 RESERVED Reserved. 0x0 R/W 10 B10L_EEE 10BASE-T1L EEE Enable. 0x0 R/W |
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