ADIN1100BCPZ-R7 datasheet(56/80 Pages) AD

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Data Sheet

ADIN1100

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Rev. B | 56 of 80

BASE-T1 Autonegotiation Advertisement Register, Bits[47:32]

Device Address: 0x07; Register Address: 0x0204, Reset: 0x0000, Name: AN_ADV_ABILITY_H

This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[47:32], specified in Clause 45.2.7.21 of Standard 802.3.

Table 73. Bit Descriptions for AN_ADV_ABILITY_H

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

AN_ADV_B10L_TX_LVL_HI_ABL

10BASE-T1L High Level Transmit Operating Mode Ability. This bit advertises

that the PHY is capable of transmitting in the high level (2.4 V p-p) transmit

operating mode. This bit is used with AN_ADV_B10L_TX_LVL_HI_REQ to

configure the 10BASE-T1L transmission level (2.4 V p-p or 1.0 V p-p). See the

AN_ADV_B10L_TX_LVL_HI_REQ bit for more details.

Pin dependent

R/W

AN_ADV_B10L_TX_LVL_HI_REQ

10BASE-T1L High Level Transmit Operating Mode Request. This bit advertises

that the PHY is requesting that high level (2.4 V p-p) transmit operating mode be

used. The transmit level is resolved as follows:

Pin dependent

R/W

If either PHY is not capable of high level transmission (and has

AN_ADV_B10L_TX_LVL_HI_ABL = 0), both PHYs must use the low voltage (1.0

V p-p) transmit operating mode.

Otherwise, if either PHY requests high level transmission (and has

AN_ADV_B10L_TX_LVL_HI_REQ = 1), both PHYs must use the high voltage

(2.4 V p-p) transmit operating mode. See IEEE P802.cg Subclause 146.6.4 for

more details.

[11:0]

RESERVED

Reserved.

0x0

BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[15:0]

Device Address: 0x07; Register Address: 0x0205, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_L

This address corresponds to the BASE-T1 autonegotiation base page ability register, Bits[15:0], of the link partner specified in Clause

45.2.7.22 of Standard 802.3. Note that the value of the AN_LP_ADV_ABILITY_M and AN_LP_ADV_ABILITY_H registers is latched when

AN_LP_ADV_ABILITY_L is read.

Table 74. Bit Descriptions for AN_LP_ADV_ABILITY_L

Bits

Bit Name

Description

Reset

Access

AN_LP_ADV_NEXT_PAGE_REQ

Link Partner Next Page Request. This bit indicates that the link partner PHY wants to send

a next page. See IEEE Standard 802.3 Subclause 98.2.1.2.9.

0x0

AN_LP_ADV_ACK

Link Partner Acknowledge (ACK). This bit indicates that the device has received the link

codeword of its link partner. See IEEE Standard 802.3 Subclause 98.2.1.2.8.

0x0

AN_LP_ADV_REMOTE_FAULT

Link Partner Remote Fault. See IEEE Standard 802.3 Subclause 98.2.1.2.7.

0x0

AN_LP_ADV_FORCE_MS

Link Partner Force Master/Slave Configuration. This bit reports the forced master/slave

configuration of the link partner, with values as follows. See IEEE Standard 802.3

Subclause 98.2.1.2.5 for more details.

0x0

0: preferred mode (AN_LP_ADV_MST is a preferred configuration).

1: forced mode (AN_LP_ADV_MST is a forced configuration).

[11:10]

AN_LP_ADV_PAUSE

Link Partner Pause Ability. This bit field reports the support of the link partner for

asymmetric and symmetric pause functions on full duplex links. See IEEE Standard 802.3

Subclause 98.2.1.2.6 for more details.

0x0

[9:5]

RESERVED

Reserved.

0x0

[4:0]

AN_LP_ADV_SELECTOR

Link Partner Selector. The value of this field reads 00001, which is the IEEE 802.3 selector

value. See IEEE Standard 802.3 Subclause 98.2.1.2.1.

0x0

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