ADAU1361BCPZ-R7 datasheet(27/78 Pages) AD

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Data Sheet

ADAU1361

RECORD SIGNAL PATH

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Rev. E | 27 of 78

Figure 31. Record Signal Path

INPUT SIGNAL PATHS

The ADAU1361 can accept both line level and microphone inputs.

The analog inputs can be configured in a single-ended or differen-

tial configuration. There is also an input for a digital microphone.

The analog inputs are biased at AVDD/2. Unused input pins should

be connected to CM.

Each of the six analog inputs has individual gain controls (boost or

cut). The input signals are mixed and routed to an ADC. The mixed

input signals can also bypass the ADCs and be routed directly

to the playback mixers. Left channel inputs are mixed before the

left ADC; however, it is possible to route the mixed analog signal

around the ADC and output it into a left or right output channel. The

same capabilities apply to the right channel and the right ADC.

Signals are inverted through the PGAs and the mixers. The result

of this inversion is that differential signals input through the PGA

are output from the ADCs at the same polarity as they are input.

Single-ended inputs that pass through the mixer but not through the

PGA are inverted. The ADCs are noninverting.

The input impedance of the analog inputs varies with the gain of

the PGA. This impedance ranges from 1.7 kΩ at the 35.25 dB gain

setting to 80.4 kΩ at the −12 dB setting. This range is shown in

Figure 22.

Analog Microphone Inputs

For microphone inputs, configure the part in either stereo pseudo-

differential mode or stereo full differential mode.

The LINN and LINP pins are the inverting and noninverting inputs

for the left channel, respectively. The RINN and RINP pins are the

inverting and noninverting inputs for the right channel, respectively.

For a differential microphone input, connect the positive signal to

the noninverting input of the PGA and the negative signal to the in-

verting input of the PGA, as shown in Figure 32. The PGA settings

are controlled with Register R8 (left differential input volume control

volume control register, Address 0x400F). The PGA must first be

enabled by setting the RDEN and LDEN bits.

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