ADAU1361BCPZ-R7 datasheet(33/78 Pages) AD

33 / 78 page

Data Sheet

ADAU1361

PLAYBACK SIGNAL PATH

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Rev. E | 33 of 78

Figure 43. Playback Signal Path

OUTPUT SIGNAL PATHS

The outputs of the ADAU1361 can be configured as a variety

of differential or single-ended outputs. All analog output pins are

capable of driving headphone or earpiece speakers. There are

selectable output paths for stereo signals or a downmixed mono

output. The line outputs can drive a load of at least 10 kΩ or can be

put into HP mode to drive headphones or earpiece speakers. The

analog output pins are biased at AVDD/2.

With a 0 dBFS digital input and AVDD = 1.8 V, the full-scale output

level is 500 mV rms; when AVDD = 3.3 V, the full-scale output level

is 920 mV rms.

Signals are inverted through the mixers and volume controls. The

result of this inversion is that the polarity of the differential outputs

and the headphone outputs is preserved. The single-ended mono

output is inverted. The DACs are noninverting.

Routing Flexibility

The playback path contains five mixers (Mixer 3 to Mixer 7) that

perform the following functions:

►

Mix signals from the record path and the DACs.

►

Mix or swap the left and right channels.

►

Mix a mono signal or generate a common-mode output.

Mixer 3 and Mixer 4 are dedicated to mixing signals from the record

path and the DACs. Each of these two mixers can accept signals

from the left and right DACs, the left and right input mixers, and the

dedicated channel auxiliary input. Signals coming from the record

path can be boosted or cut before the playback mixer.

For example, the MX4G2[3:0] bits set the gain from the output of

Mixer 2 (right record channel) to the input of Mixer 4, hence the

naming convention.

Signals coming from the DACs have digital volume attenu- ation

controls set in Register R20 (left input digital volume register, Ad-

dress 0x401A) and Register R21 (right input digital volume register,

Address 0x401B).

HEADPHONE OUTPUT

The LHP and RHP pins can be driven by either a line output driver

or a headphone driver by setting the HPMODE bit in Register

R30 (playback headphone right volume control register, Address

0x4024). The headphone outputs can drive a load of at least 16 Ω.

Separate volume controls for the left and right channels range from

−57 dB to +6 dB. Slew can be applied to all the playback volume

controls using the ASLEW[1:0] bits in Register R34 (playback pop/

click suppression register, Address 0x4028).

Capless Headphone Configuration

The headphone outputs can be configured in a capless output

configuration with the MONOOUT pin used as a dc virtual ground

reference. Figure 44 depicts a typical playback path in a capless

headphone configuration. Table 19 lists the register settings for this

configuration. As shown in this table, the MONOOUT pin outputs

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