ADAU1361BCPZ-R7 datasheet(1/78 Pages) AD

部件名	ADAU1361BCPZ-R7

功能描述	Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

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制造商	AD [Analog Devices]

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Data Sheet

ADAU1361

Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

Rev. E

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FEATURES

►

24-bit stereo audio ADC and DAC: >98 dB SNR

►

Sampling rates from 8 kHz to 96 kHz

►

Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V

►

6 analog input pins, configurable for single-ended or differential

inputs

►

Flexible analog input/output mixers

►

Stereo digital microphone input

►

Analog outputs: 2 differential stereo, 2 single-ended stereo, 1

mono headphone output driver

►

PLL supporting input clocks from 8 MHz to 27 MHz

►

Analog automatic level control (ALC)

►

Microphone bias reference voltage

►

Analog and digital I/O: 1.8 V to 3.65 V

►

I2C and SPI control interfaces

►

Digital audio serial data I/O: stereo and time-division multiplexing

(TDM) modes

►

Software-controllable clickless mute

►

Software power-down

►

32-lead, 5 mm × 5 mm LFCSP

►

−40°C to +85°C operating temperature range

APPLICATIONS

►

Smartphones/multimedia phones

►

Digital still cameras/digital video cameras

►

Portable media players/portable audio players

►

Phone accessories products

GENERAL DESCRIPTION

The ADAU1361 is a low power, stereo audio codec that supports

stereo 48 kHz record and playback at 14 mW from a 1.8 V

analog supply. The stereo audio ADCs and DACs support sample

rates from 8 kHz to 96 kHz as well as a digital volume control.

The ADAU1361 is ideal for battery-powered audio and telephony

applications.

The record path includes an integrated microphone bias circuit and

six inputs. The inputs can be mixed and muxed before the ADC,

or they can be configured to bypass the ADC. The ADAU1361

includes a stereo digital microphone input.

The ADAU1361 includes five high power output drivers (two differ-

ential and three single-ended), supporting stereo head-phones, an

earpiece, or other output transducer. AC-coupled or capless config-

urations are supported. Individual fine level controls are supported

on all analog outputs. The output mixer stage allows for flexible

routing of audio.

The serial control bus supports the I2C and SPI protocols. The seri-

al audio bus is programmable for I2S, left-/right-justified, and TDM

modes. A programmable PLL supports flexible clock generation for

all standard integer rates and fractional main clocks from 8 MHz to

27 MHz.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

类似零件编号 - ADAU1361BCPZ-R7

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