ADAU1361BCPZ-R7 datasheet(46/78 Pages) AD

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Data Sheet

ADAU1361

CONTROL REGISTERS

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Table 29. Digital Microphone/Jack Detection Control Register (Continued)

Bits

Bit Name

Description

[5:4]

JDFUNC[1:0]

JACKDET/MICIN pin function. Enables or disables the jack detect function or

configures the pin for a digital microphone input.

Setting

Pin Function

Jack detect off (default)

Jack detect on

Digital microphone input

Reserved

JDPOL

Jack detect polarity. Detects high or low signal.

0 = detect high signal (default).

1 = detect low signal.

R3: Record Power Management, 16,393 (0x4009)

This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADCs, record path

mixers, and PGAs can be set to one of four modes. These settings are normal operation, power saving mode, enhanced performance mode,

and extreme power saving mode. Each of these modes draws current from a central bias. Enhanced performance mode offers the highest

performance with the trade-off of higher power consumption.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

MXBIAS[1:0]

ADCBIAS[1:0]

RBIAS[1:0]

Reserved

Table 30. Record Power Management Register

Bits

Bit Name

Description

[6:5]

MXBIAS[1:0]

Mixer amplifier bias boost. Sets the boost level for the bias current of the record path mixers. In some cases, the boost level enhances the

THD + N performance.

Setting

Boost Level

Normal operation (default)

Boost Level 1

Boost Level 2

Boost Level 3

[4:3]

ADCBIAS[1:0]

ADC bias control. Sets the bias current for the ADCs based on the mode of operation selected.

Setting

ADC Bias Control

Normal operation (default)

Extreme power saving

Enhanced performance

Power saving

[2:1]

RBIAS[1:0]

Record path bias control. Sets the bias current for the PGAs and mixers in the record path.

Setting

Record Path Bias Control

Normal operation (default)

Reserved

Enhanced performance

Power saving

R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A)

This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

LINPG[2:0]

LINNG[2:0]

MX1EN

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