ADAU1361BCPZ-R7 datasheet(39/78 Pages) AD

39 / 78 page

Data Sheet

ADAU1361

CONTROL PORTS

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Rev. E | 39 of 78

SPI PORT

By default, the ADAU1361 is in I2C mode, but it can be put into

SPI control mode by pulling CLATCH low three times. This is done

by performing three dummy writes to the SPI port (the ADAU1361

does not acknowledge these three writes). Beginning with the

fourth SPI write, data can be written to or read from the IC. The

ADAU1361 can be taken out of SPI mode only by a full reset

initiated by power-cycling the IC.

The SPI port uses a 4-wire interface, consisting of the CLATCH,

CCLK, CDATA, and COUT signals, and it is always a subordinate

port. The CLATCH signal should go low at the beginning of a

trans-action and high at the end of a transaction. The CCLK signal

latches CDATA on a low-to-high transition. COUT data is shifted

out of the ADAU1361 on the falling edge of CCLK and should be

clocked into a receiving device, such as a microcontroller, on the

CCLK rising edge. The CDATA signal carries the serial input data,

and the COUT signal carries the serial output data. The COUT

signal remains three-state until a read operation is requested.

This allows other SPI-compatible peripherals to share the same

readback line. All SPI transactions have the same basic format

shown in Table 23. A timing diagram is shown in Figure 4. All data

should be written MSB first.

Chip Address R/W

The LSB of the first byte of an SPI transaction is a R/W bit. This bit

determines whether the communication is a read (Logic Level 1) or

a write (Logic Level 0). This format is shown in Table 22.

Table 22. ADAU1361 SPI Address and Read/Write Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

R/W

Subaddress

The 16-bit subaddress word is decoded into a location in one of

the registers. This subaddress is the location of the appropriate

word to a full 2-byte length.

Data Bytes

The number of data bytes varies according to the register being

accessed. During a burst mode write, an initial subaddress is

written followed by a continuous sequence of data for consecutive

A sample timing diagram for a single-word SPI write operation to

a register is shown in Figure 54. A sample timing diagram of a

single-word SPI read operation is shown in Figure 55. The COUT

pin goes from being three-state to being driven at the beginning of

Byte 3. In this example, Byte 0 to Byte 2 contain the addresses and

R/W bit, and subsequent bytes carry the data.

Table 23. Generic Control Word Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 41

chip_adr[6:0], R/W

subaddr[15:8]

subaddr[7:0]

data

1 Continues to end of data.

Figure 54. SPI Write to ADAU1361 Clocking (Single-Word Write Mode)

Figure 55. SPI Read from ADAU1361 Clocking (Single-Word Read Mode)

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