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ADAU1361BCPZ-R7 数据表(PDF) 9 Page - Analog Devices

部件名 ADAU1361BCPZ-R7
功能描述  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  78 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1361BCPZ-R7 数据表(HTML) 9 Page - Analog Devices

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Data Sheet
ADAU1361
SPECIFICATIONS
analog.com
Rev. E | 9 of 78
Table 5. (Continued)
Parameter
Mode
Factor
Min
Typ
Max
Unit
96 kHz mode, typ @ 96 kHz
11/fS
115
µs
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V ± 10%.
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT SPECIFICATIONS
Input Voltage High (VIH)
0.7 × IOVDD
V
Input Voltage Low (VIL)
0.3 × IOVDD
V
Input Leakage
Pull-Ups/Pull-Downs Disabled
IIH @ VIH = 3.3 V
−0.17
+0.17
µA
IIL @ VIL = 0 V
−0.17
+0.17
µA
IIL @ VIL = 0 V (MCLK pin)
−13.5
−0.5
µA
Pull-Ups Enabled
IIH @ VIH = 3.3 V
−0.7
+0.7
µA
IIL @ VIL = 0 V
−13.5
−0.5
µA
Pull-Downs Enabled
IIH @ VIH = 3.3 V
2.7
8.3
µA
IIL @ VIL = 0 V
−0.18
+0.18
µA
Input Capacitance
5
pF
OUTPUT SPECIFICATIONS
Output Voltage High (VOH)
IOH = 2 mA @ 3.3 V, 0.85 mA @ 1.8 V
0.8 × IOVDD
V
Output Voltage Low (VOL)
IOL = 2 mA @ 3.3 V, 0.85 mA @ 1.8 V
0.1 × IOVDD
V
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V ± 10%.
Table 7. Digital Timing
Parameter
Limit
Unit
Description
tMIN
tMAX
MAIN CLOCK
tMP
74
488
ns
MCLK period, 256 × fS mode.
tMP
37
244
ns
MCLK period, 512 × fS mode.
tMP
24.7
162.7
ns
MCLK period, 768 × fS mode.
tMP
18.5
122
ns
MCLK period, 1024 × fS mode.
SERIAL PORT
tBIL
5
ns
BCLK pulse width low.
tBIH
5
ns
BCLK pulse width high.
tLIS
5
ns
LRCLK setup. Time to BCLK rising.
tLIH
5
ns
LRCLK hold. Time from BCLK rising.
tSIS
5
ns
DAC_SDATA setup. Time to BCLK rising.
tSIH
5
ns
DAC_SDATA hold. Time from BCLK rising.
tSOD
50
ns
ADC_SDATA delay. Time from BCLK falling in main or subordinate mode. Full range
of IOVDD.
25
ns
ADC_SDATA delay. Time from BCLK falling in main or subordinate mode. IOVDD =
3.3 V ± 10%.
SPI PORT
fCCLK
10
MHz
CCLK frequency.
tCCPL
10
ns
CCLK pulse width low.



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