数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADAU1361BCPZ-R7 数据表(PDF) 10 Page - Analog Devices

部件名 ADAU1361BCPZ-R7
功能描述  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  78 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1361BCPZ-R7 数据表(HTML) 10 Page - Analog Devices

Back Button ADAU1361BCPZ-R7 Datasheet HTML 6Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 7Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 8Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 9Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 10Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 11Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 12Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 13Page - Analog Devices ADAU1361BCPZ-R7 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 78 page
background image
Data Sheet
ADAU1361
SPECIFICATIONS
analog.com
Rev. E | 10 of 78
Table 7. Digital Timing (Continued)
Parameter
Limit
Unit
Description
tMIN
tMAX
tCCPH
10
ns
CCLK pulse width high.
tCLS
5
ns
CLATCH setup. Time to CCLK rising.
tCLH
10
ns
CLATCH hold. Time from CCLK rising.
tCLPH
10
ns
CLATCH pulse width high.
tCDS
5
ns
CDATA setup. Time to CCLK rising.
tCDH
5
ns
CDATA hold. Time from CCLK rising.
tCOD
50
ns
COUT three-stated. Time from CLATCH rising.
I2C PORT
fSCL
400
kHz
SCL frequency.
tSCLH
0.6
µs
SCL high.
tSCLL
1.3
µs
SCL low.
tSCS
0.6
µs
Setup time; relevant for repeated start condition.
tSCH
0.6
µs
Hold time. After this period, the first clock is generated.
tDS
100
ns
Data setup time.
tSCR
300
ns
SCL rise time.
tSCF
300
ns
SCL fall time.
tSDR
300
ns
SDA rise time.
tSDF
300
ns
SDA fall time.
tBFT
0.6
µs
Bus-free time. Time between stop and start.
DIGITAL MICROPHONE
RLOAD = 1 MΩ, CLOAD = 14 pF.
tDCF
10
ns
Digital microphone clock fall time.
tDCR
10
ns
Digital microphone clock rise time.
tDDV
22
30
ns
Digital microphone delay time for valid data.
tDDH
0
12
ns
Digital microphone delay time for data three-stated.
DIGITAL TIMING DIAGRAMS
Figure 2. Serial Input Port Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com