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TMP92FD54AI 数据表(PDF) 4 Page - Toshiba Semiconductor |
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TMP92FD54AI 数据表(HTML) 4 Page - Toshiba Semiconductor |
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4 / 84 page  2006-01-27 92FD54AI-4 TMP92FD54AI Figure 1 TMP92FD54AI block diagram PORT0 PORT4 INTERRUPT CONTROLLER SERIAL BUS I/F Channel 0 SERIAL BUS I/F Channel 1 SERIAL EXP.I/F PM0( SS /A8) PM1(MOSI/A9) PM2(MISO/A10) PM3(SECLK/A11) PN0(SCK0) PN1(SO0/SDA0) PN2(SI0/SCL0) PN3(SCK1/A12) PN4(SO1/SDA1/A13) PN5(SI1/SCL1/A14) P00toP07 (D0toD7) P40toP47 (A0toA7) INT0 NMI RESET AM0 AM1 TEST0 TEST1 PORT7 P70( RD ) P71( WR ) P73( CS ) P74 P75( WAIT ) CLK IX IY IZ SP L H E D C B A W XSP XIZ XIY XIX XHL XDE XBC XWA 900/H1 CPU F SR 32 bits P C 32KB RAM 512KB Flash E2PROM SERIAL I/O Channel 0 SERIAL I/O Channel 1 10-BIT 12CH A/D CONVERTER 8BIT TIMER (TIMER0) 8BIT TIMER (TIMER1) 8BIT TIMER (TIMER2) 8BIT TIMER (TIMER3) 8BIT TIMER (TIMER4) 8BIT TIMER (TIMER5) 8BIT TIMER (TIMER6) 8BIT TIMER (TIMER7) CAN CONTROLLER WATCH-DOG TIMER 16BIT TIMER (TIMER8) 16BIT TIMER (TIMERA) REAL TIME CLOCK (RTC) OSC RTC Regulator (TO7/INT4)PC5 (TI4/INT3)PC3 (TO3/INT2)PC2 (TO5)PC4 (TI0/INT1)PC0 (TO1)PC1 (TX)PF6 (RX)PF7 VREFL VREFH ADVSS ADVCC PG0toPG7 (AN0toAN7) PL0toPL3 (AN8toAN11) (RXD0)PF1 (TXD0)PF0 (RXD1)PF4 (TXD1)PF3 (SCLK0/ CTS0 )PF2 (SCLK1/ CTS1 )PF5 (TI8/WUINT0/INT5/A16) PD0 (TI9/WUINT1/INT6/A17) PD1 (TO8/WUINT2/A18) PD2 (TO9/WUINT3/A19) PD3 (TIA/WUINT4/INT7/A20) PD4 (TIB/WUINT5/A21) PD5 (TOA/WUINT6/A22) PD6 (TOB/WUINT7/A23) PD7 REGOUT XT1 XT2 X1 X2 DVSS[6] DVCC5[5] REGEN DVCC3[3] SERIAL BUS I/F Channel 2 PM4(SCK2) PN6(SO2/SDA2/A15) P72(SI2/SCL2) 3K-byte Mask ROM (for Flash boot mode) |
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