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TMP92FD54AI 数据表(PDF) 76 Page - Toshiba Semiconductor

部件名 TMP92FD54AI
功能描述  CMOS 32-bit Micro-controller
PDF  84 Pages
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制造商  TOSHIBA [Toshiba Semiconductor]
网页  http://www.semicon.toshiba.co.jp/eng
标志 TOSHIBA - Toshiba Semiconductor

TMP92FD54AI 数据表(HTML) 76 Page - Toshiba Semiconductor

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2006-01-27
92FD54AI-76
TMP92FD54AI
5.4 AD Conversion Characteristics
Symbol
Parameter
Min
Typ
MAX
Unit
VREFH
Analog reference voltage(＋)
VCC5-0.2
VCC5
VCC5
VREFL
Analog reference voltage(－)
VSS5
VSS5
VSS5
AVCC
AD Converter Power Supply Voltage
VCC5-0.2
VCC5
VCC5
AVSS
AD Converter Ground
VSS5
VSS5
VSS5
AVIN
Analog Input Voltage
VREFL
VREFH
V
Analog Current for analog reference voltage
<VREFON>=1
0.8
1.2
mA
IREF
<VREFON>=0
0.02
5
uA
ET
Total error
(excluding quantize error)
±3.0
LSB
Note) “LSB” is the UNIT which means the resolution of AD CONVERTER. (+/- 3 LSB = 3 * VCC/1024 = +/-15mV)
5.5 Event Counter (TI0, TI4, TI8, TI9, TIA, TIB)
Variable
20MHz
16MHz
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Clock Cycle
tVCK
8T+100
500
600
ns
Clock Low Width
tVCKL
4T+40
240
290
ns
Clock High Width
tVCKH
4T+40
240
290
ns
5.6 Serial Channel Timing
(1) SCLK Input mode (I/O Interface mode)
Variable
20MHz
16MHz
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
SCLK Cycle
tSCY
16T
0.8
1.0
us
Output Data → SCLK Rise
tOSS
tSCY/2-4T
-110
90
140
SCLK Rise → Output Data Hold
tOHS
tSCY/2+2T
500
625
SCLK Rise → Input Data Hold
tHSR
3T+10
160
197.5
SCLK Rise → Input Data Valid
tSRD
tSCY
800
1000
ns
(2) SCLK Output mode (I/O Interface mode)
Variable
20MHz
16MHz
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
SCLK Cycle (programmable)
tSCY
16T
8192T
0.8
409.6
1.0
512
us
Output Data → SCLK Rise
tOSS
tSCY/2-40
360
460
SCLK Rise → Output Data Hold
tOHS
tSCY/2-40
360
460
SCLK Rise → Input Data Hold
tHSR
0
0
0
SCLK Rise → Input Data Valid
tSRD
tSCY/2-T
-180
570
757.5
ns



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