TMP92FD54AI datasheet(56/84 Pages) TOSHIBA

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92FD54AI-56

2006-01-27

TMP92FD54AI

Also, if auto operation terminates abnormally or if the mode which has been

set is cleared by the issuing of a command, the device will re-enter Read Mode

due to the CPU being reset. Note that if the device is halted by a hardware

reset during auto operation, the flash memory data cannot be rewritten

correctly. In this case it is necessary to rewrite the data.

For details of the CPU’s Reset operation, please refer to Section 4.2.1,

Reset

operation. After being reset by a designated reset input, the CPU reads reset

vector data from the flash memory and starts post-Reset operation.

4) Auto Program

Writing to the flash memory involves changing the contents of cells containing 1 to

0. You cannot change 0 to 1. The only way to write 1 to a cell is to erase all the cells.

In User Boot Mode or during RAM transfer, data is written to the flash memory in

units of 32 bits (long words). Auto Program operation is begun when a program

address and program data (in units of long words) are latched in the fourth Bus

Write cycle of the Command cycle. Auto programming starts when the flash

memory has latched the program data. Since data is written in units of 32 bits, the

program address must be incremented by 4.

Once program operation has begun, programming and program verification are

automatically performed inside the chip. The status of an Auto Program operation

can be checked by monitoring the Hardware Sequence flags (see Table 4.4.6).

During Auto Program operation, the device will not accept any command

sequences input. To stop operation, use a hardware reset. Note that if operation is

interrupted, data cannot be written to the flash memory correctly.

Data cannot be written to addresses within a protected block. If this is attempted,

the device will not execute Auto Program but will enter Read Mode. If Auto

Program terminates normally, the device will automatically re-enter Read Mode. If

Auto Program terminates in error, the flash memory will be locked into that mode

and will not re-enter Read Mode. This status can be confirmed by inspecting the

Hardware Sequence flag.

To return to Read Mode, it is necessary to reset the flash memory or the device

using the Reset command or a hardware reset. In this case, because a write to the

protected block address generated an error, it is recommended that the block which

contains the bad address not be used or that the device itself not be used.

5) Auto Chip Erase

Auto Chip Erase operation starts after the sixth Bus Write cycle of the Command

cycle has ended. Once it has started, all flash memory addresses inside the chip are

automatically programmed to 0; this is followed by the execution of Erase and

Erase Verify. The status of an Auto Chip Erase operation can be checked by

monitoring the Hardware Sequence flags (see Table 4.4.5). During an Auto Chip

Erase operation, the device cannot accept any command sequences input. To stop

operation, use a hardware reset. Note that if operation is interrupted, data cannot

be erased correctly and hence the Auto Chip Erase must be re-executed.

TMP92FD54AI 数据表(PDF) 56 Page - Toshiba Semiconductor

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