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TMP92FD54AI 数据表(PDF) 32 Page - Toshiba Semiconductor |
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TMP92FD54AI 数据表(HTML) 32 Page - Toshiba Semiconductor |
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32 / 84 page  2006-01-27 92FD54AI-32 TMP92FD54AI Table 4.3.3 Single Boot program transfer format (for RAM transfer) Number of bytes transferred Data transferred from the controller to the device Baud rate Data transferred from the device to the controller BOOT ROM 1st byte Serial operation mode and baud rate settings For UART 86H Desired baud rate (Table 4.3.1(a)) ⎯ 2nd byte ⎯ ACK response for Serial Operation Mode For UART If normal (can be set) 86H (If the device determines that the baud rate cannot be set, it will stop operating.) 3rd byte Operation command data (10H) ⎯ 4rth byte ⎯ ACK response for operation command *1 If normal 10H If abnormal × 1H If communications error occurs × 8H 5th byte ∼ 16th byte PASSWORD data (12 bytes) (08FEF4H to 08FEFFH) ⎯ 17th byte CHECKSUM value for bytes 5 to 16 ⎯ 18th byte ⎯ ACK response to CHECKSUM value *1 If normal 10H If abnormal 11H If communications error occurs 18H 19th byte RAM storage start address 31 to 24 ⎯ 20th byte RAM storage start address 23 to 16 ⎯ 21st byte RAM storage start address 15 to 8 ⎯ 22nd byte RAM storage start address 7 to 0 ⎯ 23rd byte RAM storage bytes 15 to 8 ⎯ 24th byte RAM storage bytes 7 to 0 ⎯ 25th byte CHECKSUM value for bytes 19 to 24 ⎯ 26th byte ⎯ ACK response for CHECKSUM value *1 If normal 10H If abnormal 11H If communications error occurs 18H 27th byte ∼ mth byte RAM storage data ⎯ (m + 1) th byte CHECKSUM value for bytes 27 to m ⎯ (m + 2) th byte ⎯ ACK response for CHECKSUM value *1 If normal 10H If abnormal 11H If communications error occurs 18H RAM (m + 3) th byte ⎯ JUMP RAM storage start address *1: After returning an abnormal response the device waits for the operation command (third byte). In I/O Interface Mode this ACK response is not generated. *2: Write your program so that the data in bytes 19 to 25 is stored within the RAM address area 000400H to 0083FFH. |
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