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TMP92FD54AI 数据表(PDF) 7 Page - Toshiba Semiconductor |
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TMP92FD54AI 数据表(HTML) 7 Page - Toshiba Semiconductor |
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7 / 84 page ![]() 2006-01-27 92FD54AI-7 TMP92FD54AI Pin name Pin number Number of pins In/Out Function PD4 TIA INT7 A20 WUINT4 45th 1 in/out in in out in Port D4: I/O port. Timer input A: Input pin for timer A Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge. Address: Address bus 20. Wake up input 4: Wake up request pin with programmable rising, falling or both falling and rising edge. PD5 TIB A21 WUINT5 46th 1 in/out in out in Port D5: I/O port. Timer input B: Input pin for timer B. Address: Address bus 21. Wake up input 5: Wake up request pin with programmable rising, falling or both falling and rising edge. PD6 TOA A22 WUINT6 47th 1 in/out out out in Port D6: I/O port. Timer output A: Output pin for timer A. Address: Address bus 22. Wake up input 6: Wake up request pin with programmable rising, falling or both falling and rising edge. PD7 TOB A23 WUINT7 48th 1 in/out out out in Port D7: I/O port. Timer output B: Output pin for timer B. Address: Address bus 23. Wake up input 7: Wake up request pin with programmable rising, falling or both falling and rising edge. PF0 TXD0 12th 1 in/out out Port F0: I/O port. Serial interface channel 0: Transmission data. PF1 RXD0 11th 1 in/out in Port F1: I/O port. Serial interface channel 0: Receive data. PF2 SCLK0 CTS0 10th 1 in/out in/out in Port F2: I/O port. Serial interface channel 0: Clock input/output. Serial interface channel 0: Data ready to send. (Clear-to-send) PF3 TXD1 9th 1 in/out out Port F3: I/O port. Serial interface channel 1: Transmission data. PF4 RXD1 8th 1 in/out in Port F4: I/O port. Serial interface channel 1: Receive data. PF5 SCLK1 CTS1 7th 1 in/out in/out in Port F5: I/O port. Serial interface channel 1: Clock input/output. Serial interface channel 1: Data ready to send. (Clear-to-send) PF6 TX 6th 1 in/out out Port F6: I/O port. CAN: Transmission data. PF7 RX 5th 1 in/out in Port F7: I/O port. CAN: Receive data. PG0..PG7 AN0..AN7 89 th …96th 8 in in Port G: Input-only port. Analog input 0 to 7: AD converter input pins. PL0..PL3 AN8..AN1 1 97th...100th 4 in in Port L0 to L3: Input-only port. Analog input 8 to 11: AD converter input pins. PM0 SS A8 16th 1 in/out in out Port M0: I/O port. SEI: Slave select input. Address: Address bus 8. PM1 MOSI A9 17th 1 in/out in/out out Port M1: I/O port. SEI: Master output, slave input. Address: Address bus 9. PM2 MISO A10 18th 1 in/out in/out out Port M2: I/O port. SEI: Master input, slave output. Address: Address bus 10. PM3 SECLK A11 19th 1 in/out in/out out Port M3: I/O port. SEI: Clock input/output. Address: Address bus 11. PM4 SCK2 14th 1 in/out in/out Port M4: I/O port. SBI channel 2: Clock input/output at SIO mode. PN0 SCK0 59th 1 in/out in/out Port N0: I/O port. SBI channel 0: Clock input/output at SIO mode. INT7 WUINT4 WUINT5 WUINT6 WUINT7 |
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