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TMP92FD54AI 数据表(PDF) 78 Page - Toshiba Semiconductor |
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TMP92FD54AI 数据表(HTML) 78 Page - Toshiba Semiconductor |
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78 / 84 page  2006-01-27 92FD54AI-78 TMP92FD54AI 5.8 Serial bus interface 5.8 Serial bus interface I2CBUS-AC-SPEC TABLE MIN MAX MIN MAX MIN MAX 1 SCL clock frequency ｆｓｃｌ KHz 0 400 0 100 0 fc/(2 n+8) 2 Hold time (repeated) START condition. After this period, the first clock pulse is generated. ｔ HD；STA ns 650 - 4500 - 2 n-1/fc - 3 LOW period of the SCL clock ｔ LOW ns 1300 - 4700 - 2 n-1/fc - 4 HIGH period of the SCL clock ｔ HIGH ns 600 - 4000 - (2 n-1+8)/fc - 5 Set-up time for a repeated START condition ｔ SU；STA ns 6 Data hold time: for CBUS compatible masters for I2C-bus devices ｔ HD；DAT ns 0 900 0 3450 0 6/fc 7 Data set-up time ｔ SU；DAT ns 100 - 250 - (2 n-1-6)/fc - ７’ Data set-up time (The case in the first bit after transfer ) ｔ SU；1stDAT ↑ ↑↑↑↑ (2 n-1-12)/fc - 8 Rise time of both SDA and ACL signals (*1) ｔ r ns - 300 (receive) - 1000 (receive) - 9 Fall time of both SDA and ACL signals ｔｆ ns - 300 - 300 - 10 Set-up time for STOP condition ｔ SU；STO ns 950 - 4200 - (2 n-1+12)/fc - 11 Bus free time between a STOP and START condition ｔ BUF ns 12 Capacitive load for each cus line Cb pF 400 400 400 13 Noise margin at the LOW level for each connected device (including hysteresis) VnL v 0.2VDD5 -0.2VDD5 -0.2VDD5 - 14 Noise margin at the HIGH level for each connected device (including hysteresis) VnH v 0.2VDD5 -0.2VDD5 - 0.2VDD5 - 15 Pulse width of spikes which must be suppressed by the input filter tsp ns 0 50 n/a n/a n/a n/a Note 1 All values referred to VIHmin and VILmax levels. (fc=２０ＭＨｚ) No PARAMETER SYMBOL UNIT (fc=System clock) by software by software ４００KHｚ 100KHz Existing rate by software by software by software by software SDA SCL LOW ｔ f ｔ HD:STA ｔ HD:DAT ｔ r ｔ SU:DAT ｔ f ｔ HIGH ｔ SU:STA ｔ HD:STA ｔ SP ｔ SU:STO ｔ r ｔ BUF ｔ S Sr P S S : Start P :Stop Sr : ReStart SU:1stDAT ｔ I2BUS CLK AC SPEC : Tr (Transmitter selection ) Vih SCLK T-Low Tr T-High SCK(0001 - 0110) 2*(n-1)/fc (2*(n-1)+8)/fc SCK(1111) :100KHz 100/fc 100/fc SCK(1000) :400KHz 32/fc 18/fc Tr 0 to 2/fc 2/fc to 4/fc 4/fc to 6/fc 6/fc to 8/fc 8/fc to 10/fc …. SCK(0001 - 0110) T-R 0 4/fc 8/fc …. SCK(1111) :100KHz T-R 0 4/fc 8/fc …. SCK(1000) :400KHz T-R 0 2/fc 4/fc 6/fc 8/fc …. T-period = T-Low + T-R + T-High Example:in the case of fc=20MHz, SCK3,2,1,0=(0001), Tr=200ns 1) Tr=200ns so T-R=4/fc 2) T-period = 2*(n-1)/fc + 4/fc + (2*(n-1)+8)/fc =76/fc =3.8us *1) |
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