TMP92FD54AI datasheet(13/84 Pages) TOSHIBA

13 / 84 page

2006-01-27

92FD54AI-13

TMP92FD54AI

The input pin levels on AM0, AM1, TEST0 and TEST1, which are set externally

during a Reset, determine the operation mode - either Single-Chip Mode, Single-Boot

Mode.

For all operation modes, the CPU will start operating in the selected mode on

completion of the reset. The input pin levels are set before the reset is completed. Once

the mode has been set, make sure that the input pin levels do not change during

operation. The following table shows how each operation mode is set. The state

diagram beneath the table shows the various possible mode transitions.

Table 4.2.2 Operation mode pin settings

Input Pins

Operation Mode

RESET

AM1

AM0

TEST1

TEST0

(1)

Single-Chip Mode (Normal & User Boot)

(2)

Single Boot Mode

Figure 4.2.1 Mode transition diagram

4.2.1

Reset operation

To reset the device, hold the RESET input Low (= 0) for at least 20 system clock

periods while the power supply voltage is within the rated operating range and the

internal high-frequency oscillator is oscillating stably. When the device is

operating at 20 MHz, this period will by equal to 4

µs. For details please refer to

the section entitled Reset Operation in TMP92CD54I User’s Manual.

On-Board

Programming Mode

/ RESET = 0

RESET = 0

(2)

(1)

Switching set

by the user

Single-Chip Mode

Reset state

Normal Mode

User Boot

Mode

Single

Boot Mode

Numbers in ( ) indicate the column row in the above table in which the input pin levels for the

mode setting are shown.

TMP92FD54AI 数据表(PDF) 13 Page - Toshiba Semiconductor

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