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ST10F271 数据表(PDF) 53 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 173 page  ST10F271 Interrupt system 53/173 Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts. 9.1 X-Peripheral interrupt The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints on the implementation of the new functionality. In particular, the additional X- Peripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt management is proposed. In the next Figure 9, the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four X-interrupt available vectors (XP0INT, XP1INT, XP2INT and XP3INT). It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each: ● Byte High XIRxSEL[15:8] Interrupt Enable bits ● Byte Low XIRxSEL[7:0] Interrupt Flag bits When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh See Paragraph 9.1 XP0IR XP0IE XP0INT 00’0100h 40h See Paragraph 9.1 XP1IR XP1IE XP1INT 00’0104h 41h See Paragraph 9.1 XP2IR XP2IE XP2INT 00’0108h 42h See Paragraph 9.1 XP3IR XP3IE XP3INT 00’010Ch 43h Table 28. Interrupt sources (continued) Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number |
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