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ST10F271 数据表(PDF) 82 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 173 page ![]() System reset ST10F271 82/173 Figure 19. Asynchronous hardware RESET (EA = 1) RSTF P0[15:13] P0[12:2] transparent transparent not t. P0[1:0] not t. not transparent FLARST ≤ 2 TCL RST ≤ 1 ms Latching point of Port0 for system start-up configuration RPD IBUS-CS 1) not transparent not transparent Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500ns to take into account of Input Filter on RSTIN pin (After Filter) RSTIN ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns 7 TCL (internal) 3..4 TCL not t. not t. |
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