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ST10F271 数据表(PDF) 87 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 87 Page - STMicroelectronics |
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87 / 173 page  ST10F271 System reset 87/173 Figure 22. Synchronous short / long hardware RESET (EA = 0) P0[15:13] not transparent RSTF P0[12:2] transparent not t. P0[1:0] not t. not transparent RST 1024 TCL 3..8 TCL3) 2) VRPD > 2.5V Asynchronous Reset not entered 200mA Discharge RPD RSTOUT At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset (After Filter) RSTIN < 1032 TCL ≤4 TCL5) 4) ≤12 TCL 1) ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns ALE 8 TCL 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation) the asynchronous reset is then immediately entered. 4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). Notes: 3. 3 to 8 TCL depending on clock source selection. 8 TCL not t. |
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