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ST10F271 数据表(PDF) 36 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 173 page  Internal Flash memory ST10F271 36/173 5.5.4 Flash non volatile access protection register 1 low 5.5.5 Flash non volatile access protection register 1 high Table 20. Flash non volatile access protection register 0 Bit Function ACCP Access Protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash Module address space, unless the current instruction is fetched from IFlash. DBGP Debug Protection This bit, if erased at 1, allows to by-pass all the protections using the Debug features through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash Test Modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. FNVAPR1L (0x08 DFBC) NVR Delivery value:: FFFFh 15 14 13 12 11 10 987 65432 10 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 21. Flash non volatile access protection register 1 low Bit Function PDS(15:0) Protections Disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. FNVAPR1H (0x08 DFBE) NVR Delivery value: FFFFh 15 14 13 12 11 10 987 65432 10 PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 22. Flash non volatile access protection register 1 high Bit Function PEN15-0 Protections Enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0. |
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