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ST10F271 数据表(PDF) 55 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 173 page  ST10F271 Interrupt system 55/173 9.2 Exception and error traps list Table 30 shows all of the possible exceptions or error conditions that can arise during run- time. Note: * - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets. - Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level. - The resets have the highest priority level and the same trap number. - The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced. ASC1 Error x PLL Unlock / OWD x PWM1 Channel 3...0 xx Table 29. X-Interrupt detailed mapping (continued) XP0INT XP1INT XP2INT XP3INT Table 30. Trap priorities Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap* Priority Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 00’0000h 00’0000h 00’0000h 00h 00h 00h III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008h 00’0010h 00’0018h 02h 04h 06h II II II Class B Hardware Traps: Undefined Opcode MAC Interruption Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC MACTRP PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028h 00’0028h 00’0028h 00’0028h 00’0028h 00’0028h 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah I I I I I I Reserved [002Ch - 003Ch] [0Bh - 0Fh] Software Traps TRAP Instruction Any 0000h – 01FCh in steps of 4h Any [00h - 7Fh] Current CPU Priority |
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