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ST10F271 数据表(PDF) 97 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 173 page ![]() ST10F271 System reset 97/173 Figure 31. System reset circuit Figure 32. Internal (simplified) reset circuitry RPD RSTIN VDD + C0 R0 External Hardware VDD R2 + C1 R1 D2 D1 o.d. External Reset Source Open Drain Inverter VDD ST10F271 RSTOUT EINIT Instruction Trigger Clr Clock Reset State Machine Internal Reset Signal Reset Sequence (512 CPU Clock Cycles) SRST instruction watchdog overflow RSTIN VDD BDRSTEN VDD RPD Weak Pulldown (~200 µA) From/to Exit Powerdown Circuit Asynchronous Reset Clr Q Set |
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