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ST10F271 数据表(PDF) 59 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 59 Page - STMicroelectronics |
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59 / 173 page  ST10F271 General purpose timer unit 59/173 Figure 10. Block diagram of GPT1 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs Period maximum 13.1ms 26.2ms 52.4ms 104.8 ms 209.7ms 419.4ms 838.9ms 1.678s Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz fCPU = 64 MHz Timer Input Selection T2I / T3I / T4I 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor 8 16 32 64 128 256 512 1024 Input Freq 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz Resolution 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs 16.0µs Period maximum 8.2ms 16.4ms 32.8ms 65.5ms 131.1ms 262.1ms 524.3ms 1.049s Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz fCPU = 40 MHz Timer Input Selection T2I / T3I / T4I 000b 001b 010b 011b 100b 101b 110b 111b 2n n=3...10 2n n=3...10 2n n=3...10 T2EUD T2IN CPU Clock CPU Clock CPU Clock T3IN T4IN T3EUD T4EUD GPT1 Timer T2 GPT1 Timer T3 GPT1 Timer T4 T3OTL Reload Capture U/D U/D Reload Capture Interrupt Request Interrupt Request Interrupt Request T3OUT U/D T2 Mode Control T3 Mode Control T4 Mode Control |
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