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ST10F271 数据表(PDF) 89 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 173 page  ST10F271 System reset 89/173 Figure 24. Synchronous long hardware RESET (EA = 0) 20.4 Software reset A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behavior is the same as for a synchronous short reset, except that only bits P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits P0.7...P0.2 are cleared (that is written at ‘1’). A Software reset is always taken as synchronous: there is no influence on Software Reset behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. P0[15:13] not transparent RSTF P0[12:2] transparent not t. P0[1:0] not t. not transparent RST 1024+8 TCL 3..8 TCL3) 1) V RPD > 2.5V Asynchronous Reset not entered 200 µA Discharge RPD RSTOUT At this time RSTF is sampled LOW so it is LONG reset (After Filter) RSTIN 1024+8 TCL 4 TCL2) 12 TCL ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns ≤ 500 ns ≥ 50 ns ALE 8 TCL 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). Notes: not t. transparent 3. 3 to 8 TCL depending on clock source selection. 3..4 TCL |
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