ST10F271 datasheet(105/173 Pages) STMICROELECTRONICS

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ST10F271

Power reduction modes

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In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS

during reset to exercise the EA functionality associated with the same pin: the voltage

supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz

oscillator used in conjunction with Real Time Clock module), is granted by the active main

VDD.

It must be noted that Stand-by Mode can generate problems associated with the usage of

different power supplies in CMOS systems; particular attention must be paid when the

ST10F271 I/O lines are interfaced with other external CMOS integrated circuits: if VDD of

ST10F271 becomes (for example in Stand-by Mode) lower than the output level forced by

the I/O lines of these external integrated circuits, the ST10F271 could be directly powered

through the inherent diode existing on ST10F271 output driver circuitry. The same is valid

for ST10F271 interfaced to active/inactive communication buses during Stand-by mode:

current injection can be generated through the inherent diode.

Furthermore, the sequence of turning on/off of the different voltage could be critical for the

system (not only for the ST10F271 device). The device Stand-by mode current (ISTBY) may

vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between VDD

and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this

phenomenon.

21.3.1

Entering stand-by mode

As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be

cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption.

As a consequence of a RESET event, the RAM Power Supply is switched to the internal

low-voltage supply V18SB (derived from VSTBY through the low-power voltage regulator).

The RAM interface will remain frozen until the bit XRAM2EN is set again by software

initialization routine (at next exit from main VDD power-on reset sequence).

Since V18 is falling down (as a consequence of VDD turning off), it can happen that the

XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON

by Mode switching dedicated circuit continues to confirm the RAM interface freezing,

irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when

internal V18 comes back over internal stand-by reference V18SB.

If internal V18 becomes lower than internal stand-by reference (V18SB) of about 0.3 to 0.45V

with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a

temporary drop on internal V18 voltage versus internal V18SB during normal code execution,

no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be

accessed).

The ST10F271 Core module, generating the RAM control signals, is powered by internal

V18 supply; during turning off transient these control signals follow the V18, while RAM is

switched to V18SB internal reference. It could happen that a high level of RAM write strobe

from ST10F271 Core (active low signal) is low enough to be recognized as a logic “0” by the

RAM interface (due to V18 lower than V18SB): The bus status could contain a valid address

for the RAM and an unwanted data corruption could occur. For this reason, an extra

interface, powered by the switched supply, is used to prevent the RAM from this kind of

potential corruption mechanism.

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