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ST10F271 数据表(PDF) 116 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 116 Page - STMicroelectronics |
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116 / 173 page  Register set ST10F271 116/173 Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset Value depends on different triggered reset event. 3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes. 23.2 XBus registers The following table lists all XBus registers which are implemented in the ST10F271 ordered by their name. Note: The XBus registers are not bit-addressable. XPERCON b F024h E 12h XPER configuration register - - 05h ZEROS b FF1Ch 8Eh Constant value 0’s register (read only) 0000h Table 52. List of special function registers (continued) Name Physical address 8-bit address Description Reset value Table 53. List of XBus registers Name Physical address Description Reset value CAN1BRPER EF0Ch CAN1: BRP extension register 0000h CAN1BTR EF06h CAN1: Bit timing register 2301h CAN1CR EF00h CAN1: CAN control register 0001h CAN1EC EF04h CAN1: error counter 0000h CAN1IF1A1 EF18h CAN1: IF1 arbitration 1 0000h CAN1IF1A2 EF1Ah CAN1: IF1 arbitration 2 0000h CAN1IF1CM EF12h CAN1: IF1 command mask 0000h CAN1IF1CR EF10h CAN1: IF1 command request 0001h CAN1IF1DA1 EF1Eh CAN1: IF1 data A 1 0000h CAN1IF1DA2 EF20h CAN1: IF1 data A 2 0000h CAN1IF1DB1 EF22h CAN1: IF1 data B 1 0000h CAN1IF1DB2 EF24h CAN1: IF1 data B 2 0000h CAN1IF1M1 EF14h CAN1: IF1 mask 1 FFFFh CAN1IF1M2 EF16h CAN1: IF1 mask 2 FFFFh CAN1IF1MC EF1Ch CAN1: IF1 message control 0000h CAN1IF2A1 EF48h CAN1: IF2 arbitration 1 0000h CAN1IF2A2 EF4Ah CAN1: IF2 arbitration 2 0000h CAN1IF2CM EF42h CAN1: IF2 command mask 0000h |
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