ST10F271 datasheet(153/173 Pages) STMICROELECTRONICS

153 / 173 page

ST10F271

Electrical characteristics

153/173

Figure 50.

External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE

t43

ALE fall. edge to RdCS, WrCS

(no RW delay)

– 5.5 + tA

–

– 5.5 + tA

–ns

t44

Address float after RdCS,

WrCS (with RW delay)1

–

1.5

–

1.5

t45

Address float after RdCS,

WrCS (no RW delay)1

–

TCL + 1.5

t46

RdCS to Valid Data In

(with RW delay)

–4 + tC

–

2TCL – 21 + tC

t47

RdCS to Valid Data In

(no RW delay)

–16.5 + tC

–

3TCL – 21 + tC

t48

RdCS, WrCS Low Time

(with RW delay)

15.5 + tC

–

2TCL – 9.5 + tC

–ns

t49

RdCS, WrCS Low Time

(no RW delay)

28 + tC

–

3TCL – 9.5 + tC

–ns

t50

Data valid to WrCS

10 + tC

–

2TCL – 15 + tC

–ns

t51

Data hold after RdCS

0–

–

t52

Data float after RdCS1

–

16.5 + tF

–

2TCL – 8.5 + tF

t54

Address hold after

RdCS, WrCS

6 + tF

–

2TCL – 19 + tF

–ns

t56

Data hold after WrCS

6 + tF

–

2TCL – 19 + tF

–ns

Table 77.

Multiplexed bus timings (continued)

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU Clock

1/2 TCL = 1 to 64MHz

min.

max.

min.

max.

Data in

Address

t38

t10

Read cycle

t16

t39

t40

t25

t27

t14

t19

Address

t17

t16

t12

t13

Address

t17

t27

ALE

CSx

A23-A16

(A15-A8)

Address/data

BHE

bus (P0)

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