ADE9113 datasheet(33/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

APPLICATIONS INFORMATION

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Rev. A | 33 of 55

Crystal Selection

A 16.384 MHz crystal with a critical transconductance, gmCRITICAL,

which is 5 times smaller than the minimum transconductance spec-

ification, gm, in Table 2 can be connected across the XTALIN

and XTALOUT pins to provide a clock source for the ADE9103/

ADE9112/ADE9113. The term gmCRITICAL is defined as the mini-

mum gain required to start the crystal oscillator circuit, expressed in

mA/V, and found with Equation 3.

gmCRITICAL=4×ESRMAX×1000

× 2π×fCLK2× C0+CL2

(3)

where:

ESRMAX is the maximum ESR, expressed in ohms.

fCLK is 16.384 MHz expressed in Hz as 16.384 x 106.

C0 is the maximum shunt capacitance, expressed in farads.

CL is the load capacitance, expressed in farads.

The figures ESRMAX, C0, and CL are provided by the manufacturer

of the crystal in the associated component data sheet. Crystals with

low ESR and smaller load capacitance have a lower gmCRITICAL and

are easier to drive.

Load Capacitor Calculation

Crystal manufacturers specify the combined load capacitance

across the crystal, CL. The capacitances across the crystal are

shown in Figure 43 can be described as follows:

►

CP1 and CP2: parasitic capacitances on the clock pins formed

due to printed circuit board (PCB) traces.

►

CIN1 and CIN2: internal capacitances of the XTALIN and XTAL-

OUT pins respectively and provided in Table 2.

►

C1 and C2: selected load capacitors to get the correct combined

CL for the crystal.

The combined load capacitance, CL, at the XTALIN and XTALOUT

pins is

CL= C1+CP1+CIN1×C2+CP2+CIN2

C1+CP1+CIN1+C2+CP2+CIN2

(4)

Keep the total capacitance on both the XTALIN pin and XTALOUT

pin equal. Layout the crystal circuitry such that CP1 = CP2. Select

load capacitors such that C1 = C2.

C1+CP1+CIN1=C2+CP2+CIN2

(5)

Using Equation 4 and Equation 5, the values of C1 and C2 can be

calculated.

POWER-UP AND INITIALIZATION

PROCEDURES

At power-up or after a hardware or software reset, the following

steps must be executed for a microcontroller managing a system

formed by one or multiple ADE9103 or ADE9112 or ADE9113

devices.

Power-Up Procedure for Systems with a Single

Device

For one standalone ADE9103/ADE9112/ADE9113 device managed

by a microcontroller and clocked by a crystal, the power-up proce-

dure is as follows (see Figure 44):

1. Connect a crystal between the XTALIN and XTALOUT pins with

appropriate load capacitance.

2. Supply VDD to the ADE9103/ADE9112/ADE9113 device. To

ensure that the ADE9103/ADE9112/ADE9113 device starts

functioning correctly, the supply must reach 3.3 V − 10% in less

than 16 ms from approximately a 2.5 V level. The ADE9103/

ADE9112/ADE9113 device then starts to function.

3. The DC-to-DC converter powers up and supplies the isolated

side of the ADE9112 and ADE9113. The Σ-Δ modulators then

become functional. This process takes approximately 62 ms

to execute when the recommended capacitors on the VDDISO,

ALDOOUT, and REFOUT pins described in Table 12 are used.

After this time, the isolated side of the ADE9112 and ADE9113

is fully functional. While the ADE9103 has no isolation and

is entirely powered by VDD, the power-up timing remains the

same.

4. To determine when the ADE9103/ADE9112/ADE9113 device is

ready to accept commands, read the STATUS0 register until Bit

5 (RESET_DONE) is set to 1, which happens approximately 32

ms after the ADE9103/ADE9112/ADE9113 start to function and

indicates that the nonisolated side of the ADE9103/ADE9112/

ADE9113 is fully functional and using the default settings.

5. Initialize the registers required.

6. Set the WR_LOCK register to 0xD4 to protect the user accessi-

ble and internal configuration registers. See the Protecting the

Integrity of Configuration Registers section.

7. When the ADC conversion data is available, the ADE9103/

ADE9112/ADE9113 set the STATUS0 register, Bit 4

(COMM_UP), and begin generating a signal that is active low

at the CLKOUT/DREADY pin for 256 XTALIN cycles (15.625 µs

for XTALIN = 16.384 MHz). DREADY functionality is enabled by

default at the CLKOUT/DREADY pin.

The microcontroller reads the I_WAV, V1_WAV V2_WAV, STATUS0,

and STATUS1 registers as well as the CRC of the response packet

during every long SPI transaction. For information on SPI burst

mode, see the SPI Long Format Operation section for more infor-

mation.

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