ADE9113 datasheet(52/55 Pages) AD

52 / 55 page

Data Sheet

ADE9103/ADE9112/ADE9113

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Rev. A | 52 of 55

Table 20. Register Details (Continued)

Addr

Name

Bits Bit Name

Settings Description

Reset Access

[5:0] SNAPSHOT_COUNT[13:8]

System Timing Controller Count. Snapshot value of the system

timing controller counter used in the synchronization operation.

0x0

0x018

SNAPSHOT_COUNT_LO [7:0] SNAPSHOT_COUNT[7:0]

System Timing Controller Count. Snapshot value of the system

timing controller counter used in the synchronization operation.

0x0

0x01F

WR_LOCK

[7:0] WR_LOCK

Configuration Register Write Lock. When enabled, the lock feature

does not allow changes to writable registers of Address 0x001 to

Address 0x018.

0x5E R/W

0xD4

Lock Key. If register map is locked, the lock key value can be read.

0x5E

Unlock Key. if the register map is unlocked, any value can be

written or read from this location.

0x020

STATUS0

STATUS1X

STATUS1 Indicator. Logical OR of the STATUS1 bit fields that

have the corresponding MASK1 bit set. When this condition is

satisfied, STATUS1X asserts. To clear this bit field, the source

driving interrupt in STATUS1 must be cleared via a write 1 to clear

(W1C).

0x0

STATUS2X

STATUS2 Indicator. See the STATUS1X description but for the

STATUS2 register.

0x0

RESET_DONE

Reset Done Interrupt. Nonmaskable interrupt. This interrupt

signals that the IC is ready for configuration.

0x0

R/W1C

COM_UP

Communication Across Isolation Established. The ADE9103/

ADE9112/ADE9113 is now fully operational and ready to send

ADC waveform data.

0x0

R/W1C

CRC_CHG

a register included in the CRC has changed. This change may

be the result of user software reconfiguration; however, if this is

not the case, issue a software reset and reconfigure the ADE9103/

ADE9112/ADE9113.

0x0

R/W1C

EFUSE_MEM_ERR

eFuse Memory Error. Nonmaskable interrupt. There was an

uncorrectable error in the eFuse memory. This bit field is not

W1C, and user action is to request an eFuse memory refresh

using EFUSE_REFRESH.

0x0

SPI_CRC_ERR

SPI Write CRC Error Interrupt. A CRC error was detected on

the previous SPI command received by the ADE9103/ADE9112/

ADE9113, and this error bit is set on the SPI read response.

0x0

R/W1C

COMFLT_ERR

Isolation Communications Fault Interrupt. There was a fault in the

communication across the isolation. See the COM_FLT_TYPE and

COM_FLT_COUNT registers for more details on the error.

0x0

R/W1C

0x021

STATUS1

[7:4] RESERVED

Reserved.

0x0

V2_WAV_OVRNG

ADC V2 Channel Waveform Overrange. The V2 channel ADC

has exceeded the maximum range, and the output V2_WAV was

clamped to 7549748d.

0x0

R/W1C

V1_WAV_OVRNG

ADC V1 Channel Waveform Overrange. The V1 channel ADC

has exceeded the maximum range, and the output V1_WAV was

clamped to 7549748d.

0x0

R/W1C

I_WAV_OVRNG

ADC Current Channel Waveform Overrange. The current channel

ADC has exceeded the maximum range, and the output I_WAV

was clamped to 7549748d.

0x0

R/W1C

ADC_SYNC_DONE

SPI Write to ADC Synchronization Registers. When the

SYNC_SNAP register is written to, this interrupt triggers.

0x0

R/W1C

0x022

STATUS2

RESERVED

Reserved.

0x0

ISO_CLK_STBL_ERR

ISO ADC Clock Stability Error Detected.

0x0

R/W1C

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