ADE9113 datasheet(51/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

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Rev. A | 51 of 55

Table 20. Register Details (Continued)

Addr

Name

Bits Bit Name

Settings Description

Reset Access

V1_WAV_OVRNG

V1 Channel Overrange Interrupt Mask.

0x0

R/W

I_WAV_OVRNG

Current Channel Overrange Interrupt Mask.

0x0

R/W

ADC_SYNC_DONE

ADC Sync Done Update Interrupt Mask.

0x0

R/W

0x011

MASK2

RESERVED

Reserved.

0x0

ISO_CLK_STBL_ERR

Clock Stability Error Interrupt Mask.

0x0

R/W

ISO_PHY_CRC_ERR

Data Link CRC Error Interrupt Mask.

0x0

R/W

ISO_EFUSE_MEM_ERR

EFuse Memory Error Interrupt Mask.

0x1

R/W

ISO_DIG_MOD_V2_OVF

Digital Modulator V2 Channel Overflow Interrupt Mask.

0x0

R/W

ISO_DIG_MOD_V1_OVF

Digital Modulator V1 Channel Overflow Interrupt Mask.

0x0

R/W

ISO_DIG_MOD_I_OVF

Digital Modulator Current Channel Overflow Interrupt Mask.

0x0

R/W

ISO_TEST_MMR_ERR

Test Memory Mapped Register (MMR) Field Detected Interrupt

Mask.

0x0

R/W

0x012

CONFIG_ZX

[7:4] RESERVED

Reserved.

0x0

[3:2] ZX_EDGE_SEL

Zero-Crossing Edge Select. Select the edge behavior of the zero-

crossing (ZX) circuit.

0x0

R/W

ZX Pin Reflects the Sign of the Input Signal. The ZX pin goes high

on negative to positive ZX and low on positive to negative ZX.

Detect Zero Crossings with Positive Slope. When zero crossing

from negative to positive, a high pulse duration of 512 µs is

generated.

Detect Zero Crossings with Negative Slope. When zero crossing

from positive to negative, a high pulse duration of 512 µs is

generated.

Detect Zero Crossings with Positive or Negative Slopes.

Combines 01 and 10.

[1:0] ZX_CHANNEL_CONFIG

Zero-Crossing Channel Select.

0x0

R/W

Disable Zero-Crossing Output.

Output Zero-Crossing Function from the Current Channel on the

ZX Pin.

Output Zero-Crossing Function from the V1 Channel on the ZX

Pin.

Output Zero-Crossing Function from the V2 Channel on the ZX

Pin.

0x013

SCRATCH

[7:0] SCRATCH

Software Debug Register for Testing SPI R/W. Allows

development of SPI and user software by providing a register

that is R/W but has no other function on the chip.

0x0

R/W

0x014

SYNC_SNAP

[7:3] RESERVED

Reserved.

0x0

PREP_BROADCAST

ADC Prepare Broadcast. Set this bit only when operating with a

dedicated SPI interface and preparing to ALIGN or SNAPSHOT.

The MISO pin is tristated for the next SPI frame. This tristating of

the pad allows a ADC synchronization to be performed on several

chips simultaneously connected to single SPI main. This bit auto

clears once complete.

0x0

R/W

ALIGN

ADC Align. When the ALIGN bit is set to 1 via a broadcast SPI

write operation, all devices in the system generate ADC outputs in

the same exact moment. The bit clears itself back to 0 after one

XTALIN cycle.

0x0

R/W

SNAPSHOT

ADC Snapshot. When the SNAPSHOT bit is set to 1 via a

broadcast SPI write operation, the internal counters are latched.

The bit clears itself back to 0 after one XTALIN cycle.

0x0

R/W

0x017

SNAPSHOT_COUNT_HI [7:6] RESERVED

Reserved.

0x0

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