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Data Sheet

ADE9103/ADE9112/ADE9113

THEORY OF OPERATION

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higher frequencies where it can be removed by the digital LPF. This

noise shaping is shown in Figure 33.

Figure 33. Noise Reduction due to Oversampling and Noise Shaping in the

Analog Modulator

The bandwidth of interest is a function of the input clock frequency

and the ADC output frequency (selectable by the CONFIG_FILT

Antialiasing Filter

Figure 32 shows an analog LPF (RC) on the input to the ADC. This

filter is placed outside of the ADE9103/ADE9112/ADE9113, and its

role is to prevent aliasing. Aliasing is an artifact of all sampled

systems, as shown in Figure 34. Aliasing refers to the frequency

components in the input signal to the ADC that are higher than

half the sampling rate of the ADC and appear in the sampled

signal at a frequency less than half the sampling rate. Frequency

components more than half the sampling frequency (also known

as the Nyquist frequency, that is, 512 kHz) are imaged or folded

back down to less than 512 kHz, which happens with all ADCs,

regardless of the architecture. In Figure 34, only frequencies near

the sampling frequency of 1.024 MHz move into the bandwidth

of interest for metering, that is, 40 Hz to 3.3 kHz, or 40 Hz to

2 kHz. To attenuate the high frequency noise (near 1.024 MHz)

and prevent the distortion of the bandwidth of interest, a LPF must

be introduced. It is recommended that one RC filter with a corner

frequency of 7 kHz be used for the attenuation to be sufficiently

high at the sampling frequency of 1.024 MHz. The 20 dB per

decade attenuation of this filter is usually sufficient to eliminate the

effects of aliasing.

Figure 34. Aliasing Effects

ADC Transfer Function

All ADCs in the ADE9103/ADE9112/ADE9113 produce signed 24-

bit output codes. With a full-scale input signal of ±31.25 mV on

the current channel and ±1000 mV on the voltage channels, and

with an internal reference of 1.25 V, the ADC output code is

nominally 6,710,886 and based on the gain error, varies for each

ADE9103/ADE9112/ADE9113 around this value. Do not exceed the

nominal range of ±31.25 mV for the current channel and ±1000

mV differentially (±500 mV pseudo differentially) for the voltage

channels; ADC performance is guaranteed only for input signals

within these limits.

Approximate Output Code=VxP−VxM

VREF ×223 (1)

Approximate Output Code=32×IP−IMVREF×223 (2)

ADC Output Values

The signed 24-bit ADC output values are each stored in three

subsequent registers. The current channel ADC outputs are stored

in the I_WAV bits, Bits[23:0], the V1 voltage channel ADC outputs in

the V1_WAV bits, Bits[23:0], and the V2 voltage channel outputs in

the V2_WAVbits, Bits[23:0], see Table 19. The output frequency is

32 kHz (XTALIN/512), 8 kHz (XTALIN/2048), 4 kHz (XTALIN/4096),

2 kHz (XTALIN/8192), or 1 kHz (XTALIN/16384), and XTALIN is

16.384 MHz.

The microcontroller reads the ADC output registers one at a time

in a short transaction or all at once in a long transaction. See

the SPI Long Format Operation section and the SPI Short Format

Operation section for more information.

REFERENCE VOLTAGE

The nominal reference voltage at the REFOUT pin is 1.25 V. This

reference voltage is used for the ADCs in the ADE9103/ADE9112/

ADE9113. Because the on-chip dc-to-dc converter cannot supply

external loads, the REFOUT pin of the ADE9112 and ADE9113

cannot be overdriven by a standalone external voltage reference.

The voltage of the ADE9103/ADE9112/ADE9113 reference drifts

slightly with temperature. Table 2 lists the gain drift over tempera-

ture specification of each ADC channel. This value includes the

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