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ADE9113 数据表(PDF) 50 Page - Analog Devices |
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ADE9113 数据表(HTML) 50 Page - Analog Devices |
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50 / 55 page ![]() Data Sheet ADE9103/ADE9112/ADE9113 REGISTER DETAILS analog.com Rev. A | 50 of 55 Table 20. Register Details (Continued) Addr Name Bits Bit Name Settings Description Reset Access 0 EFUSE_REFRESH Forces a Refresh of the eFuse Memory. This bit can be used as a recovery method from a eFuse memory error without having to undertake the penalty of a hardware reset. This bit auto clears on completion of eFuse refresh. 0x0 R/W 0x009 EMI_CONFIG [7:3] RESERVED Reserved. 0x0 R [2:0] EMI_CONFIG EMI Frequency Hopping Selection. No functionality on the ADE9103. 0x3 R/W 000 Sawtooth Frequency Rising. Frequency starts at frequency defined by EMI_LO_LIMIT and ramps to higher frequency as defined by EMI_HI_LIMIT and then returns to EMI_LO_LIMIT. 001 Sawtooth Frequency Falling. Frequency starts at frequency defined by EMI_HI_LIMIT and ramps to a lower frequency as defined by EMI_LO_LIMIT and then returns to EMI_LO_LIMIT. 010 Ramp. Linear ramp up and down in frequency between the limits, EMI_LO_LIMIT and EMI_HI_LIMIT. 011 Random Hopping Frequency. The isolated power oscillator frequency varies ±63 trim codes around the calibrated center frequency of EMI_MID_LIMIT. 0x00A EMI_HI_MASK [7:0] EMI_HI_MASK Emissions Mask, High Frequency Bounds. No functionality on the ADE9103. 0x0 R/W 0x00B EMI_LO_MASK [7:0] EMI_LO_MASK Emissions Mask, Low Frequency Bounds. No functionality on the ADE9103. 0x0 R/W 0x00C EMI_HI_LIMIT [7:0] EMI_HI_LIMIT Factory Stored High Frequency Limit. This stored value corresponds to emissions of ≈420 MHz and can be used to set the EMI_xx_MASK. No functionality on the ADE9103. 0x0 R 0x00D EMI_MID_LIMIT [7:0] EMI_MID_LIMIT Factory Stored Center Frequency Value. This stored value corresponds to emissions of ≈360 MHz and can be used to set the EMI_xx_MASK. No functionality on the ADE9103. 0x0 R 0x00E EMI_LO_LIMIT [7:0] EMI_LO_LIMIT Factory Stored Low Frequency Limit. This stored value corresponds to emissions of ≈300 MHz and can be used to set the EMI_xx_MASK. No functionality on the ADE9103. 0x0 R 0x00F MASK0 7 STATUS1X STATUS1 Interrupt Mask. See the STATUS0 register details description for corresponding status bit. Mask high to allow interrupt source to drive the IRQ pin. 0x0 R/W 6 STATUS2X STATUS2 Interrupt Mask. See the STATUS0 register details description for corresponding status bit. See the STATUS1X description for mask bit functionality. 0x0 R/W 5 RESERVED Reserved. 0x0 R 4 COM_UP COM_UP Interrupt Mask. See the STATUS0 register details description for corresponding status bit. See the STATUS1X description for mask bit functionality. 0x0 R/W 3 CRC_CHG CRC_CHG Interrupt Mask. See the STATUS0 register details description for corresponding status bit. See the STATUS1X description for mask bit functionality. 0x0 R/W 2 RESERVED Reserved. 0x0 R 1 SPI_CRC_ERR SPI_CRC_ERR Interrupt Mask. See the STATUS0 register details description for corresponding status bit. See the STATUS1X description for mask bit functionality. 0x0 R/W 0 COMFLT_ERR COM_FLT_ERR Interrupt Mask. See the STATUS0 register details description for corresponding status bit. See the STATUS1X description for mask bit functionality. 0x0 R/W 0x010 MASK1 [7:4] RESERVED Reserved. 0x0 R 3 V2_WAV_OVRNG V2 Channel Overrange Interrupt Mask. 0x0 R/W |
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