ADE9113 datasheet(37/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

APPLICATIONS INFORMATION

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Rev. A | 37 of 55

SPI COMPATIBLE COMMUNICATION

The SPI port of the ADE9103/ADE9112/ADE9113 is a subordinate

device of the main communication device on the SPI bus. The

interface consists of SCLK, MOSI, MISO, and CS signals. The

serial clock for a data transfer is applied at the SCLK logic input.

All data transfer operations synchronize to the serial clock. The

maximum and minimum serial clock frequencies supported by this

interface are specified by the SCLK Frequency, fSCLK, parameter in

Table 3.

The CS logic input is the chip select input. Drive the CS input low

for the entire data transaction. Each SPI transaction consists of a

response to the previous command of up to 16 bytes on the MISO

logic and a command packet as the last 4 bytes of the transaction

on the MOSI logic. The response has both a long format, described

in SPI Long Format Operation, and a short format, described in SPI

Short Format Operation, as specified by the command packet. The

most significant bits of the word are shifted in and out first during

both long and short format operations.

Data transmission to and from the SPI port of the ADE9103/

ADE9112/ADE9113 is protected by bidirectional CRC. An 8-bit CRC

is required to be transmitted by the main communication device as

Bits[7:0] of the command packet. An incorrect CRC results in an

error. The error response can be disabled in the CONFIG0 register.

More details on the CRC calculation can be found in CRC of

Command Packet. Details of the 16-bit CRC sent by the ADE9103/

ADE9112/ADE9113 in the response can be found in the CRC of

Response Packet section.

ADE9103/ADE9112/ADE9113 devices may be connected inde-

pendently as those shown in Figure 39 or in daisy chain, as shown

in Figure 38. There is no configuration required to indicate whether

each ADE9103/ADE9112/ADE9113 device is being addressed indi-

vidually or as a member of a daisy chain. Individually addressed

devices may be issued both 32 bit short, 48 bit short and 128 bit

long format commands. Devices connected in daisy chain must

be issued commands only in the 128 bit long format. The full

SPI transaction length for daisy chain connected devices must be

exactly 128 bits multiplied by the number of daisy chain connected

devices.

The SPI port of each ADE9103/ADE9112/ADE9113 device inter-

prets the last 32 bits received by the MOSI shift register only at

the instant the CS pin transitions high. Read and write command re-

sponses are given in the next SPI response. The CMD ECHO byte

of SPI read and write responses echos the characteristics of the

command. The RWB indicates if the command was read or write.

The long bit indicates if the command was long or short format. The

RSRVD bits are reserved and wll be masked. SPI_CRC_ERR is a

flag bit that indicates a CRC error was encountered in the previous

SPI command decode when set to 1. The IRQ flag bit indicates a

pending interrupt request when set to 1.

Figure 47. SPI Command Packet Structure

Figure 48. SPI Long Read and Write Response

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