ADE9113 datasheet(40/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

APPLICATIONS INFORMATION

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Rev. A | 40 of 55

SPI Short Format Operation

A short format operation can consist of either 32 bits or 48 bits.

The command packet is always the final 32 bits or 48 bits of

the transaction on the MOSI data line. The command response is

always the first 8 bits of the MISO data line. The CRC_CCITT is

the final 16 bits only when the main transmits 48 cycles on SCLK.

A short SPI transaction is only compatible with a dedicated SPI

configuration because the daisy chain requires 128-bit responses.

The short format read operation using the ADE9103/ADE9112/

ADE9113 SPI is initiated when the main sets the CS pin low

and begins outputting the SCLK signal. Bit 31 (R/W) must be set

to 1. Bit 30 (LONG) must be cleared to 0. Bits[23:16] (ADDR)

represent the address of the register to be read or written. The

ADE9103/ADE9112/ADE9113 SPI samples data on the low to high

transitions of SCLK. During this operation, the MISO line contains

the response to the previous command packet. After the main

device complete 32 SCLK cycles or 48 SCLK cycles, it sets the

CS and SCLK lines high, and the communication ends. The MISO

data lines are set to a high impedance state when CS is not

asserted. During the following transaction, the ADE9103/ADE9112/

ADE9113 line outputs its 32-bit or 48-bit read response on MISO.

This operation contains the data in ADDR as well as ADDR + 1 as

requested in the prior operation as well as STATUS0. See Figure 51

for details of the SPI short read operation.

In the case of reading any x_WAV_x register, STATUS0 is exclud-

ed, and all 24 bits of the x_WAV_x is used instead.

The short format write operation using the ADE9103/ADE9112/

ADE9113 SPI is initiated when the main sets the CS pin low and

begins outputting the SCLK signal. Bit 31 (R/W) must be cleared

to 0. Bit 30 (LONG) must be cleared to 0. Bits[23:16] (ADDR)

represent the address of the register to be read or written. Bits[15:8]

(DATA) represents the data to be written into the address in ADDR.

The ADE9103/ADE9112/ADE9113 SPI samples data on the low to

high transitions of SCLK. During this operation, the MISO line con-

tains the response to the previous command packet. After the main

device completes 32 SCLK cycles or 48 SCLK cycles, it sets the

CS and SCLK lines high, and the communication ends. The data

lines, MOSI and MISO, go into a high impedance state. The write is

completed with a single operation. During the following transaction,

the ADE9103/ADE9112/ADE9113 line outputs its 32-bit or 48-bit

write response on MISO. This response includes a readback of the

address written to on the previous operation and STATUS0. See

Figure 52 for details of the SPI short write operation.

Figure 51. Short Format Read Transaction

Figure 52. Short Format Write Transaction

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