ADE9113 datasheet(43/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

APPLICATIONS INFORMATION

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Rev. A | 43 of 55

Table 17. Counter Initial Values as a Function of DATAPATH_CONFIG Bits

Bits[2:0], DATAPATH_CONFIG, in CONFIG_FILT

ADC Output Frequency (kHz)

(XTALIN = 16.384 MHz)

Counter C0 Initial Value

000

511

001

010

011

2047

100

101

4095

110

8191

111

16383

The value of the counter is latched on the first falling CS edge

after either ALIGN or SNAPSHOT are set in the SYNC_SNAP reg-

ister. A broadcast write to all ADE9103/ADE9112/ADE9113 devices

ensures that all the counters of every ADE9103/ADE9112/ADE9113

are latched at the same moment. The ALIGN or SNAPSHOT

bit clears itself to 0 after one XTALIN cycle. The values of the

counters offer a measure of the ADC output synchronization across

all ADE9103/ADE9112/ADE9113 devices. Ideally, the values must

be perfectly equal, indicating that all ADE9103/ADE9112/ADE9113

devices are fully synchronized. In reality, due to the uncertainty

between the SPI clock generated by the MCU and the ADE9103/

ADE9112/ADE9113 XTALIN, a ±1 count difference between coun-

ters is acceptable. The 14-bit counter is accessed via two 8-bit

registers SNAPSHOT_COUNT_HI and SNAPSHOT_COUNT_LO

as seen in Figure 55.

If the internal counter of one of the ADE9103/ADE9112/ADE9113

devices does not have a value correlated with the values of the

counters of any the other ADE9103/ADE9112/ADE9113, then the

ADC outputs of one device are no longer synchronized with the

ADC outputs from the others. The ADE9103/ADE9112/ADE9113

provides a method to resynchronize all the ADE9103/ADE9112/

ADE9113 devices through ALIGN. To perform ALIGN with a daisy-

chain SPI configuration, take the following steps:

1. Write to SYNC_SNAP of all ADE9103/ADE9112/ADE9113 devi-

ces to prepare for an ALIGN. Set PREP_BROADCAST = 0,

ALIGN = 1, and SNAPSHOT = 0.

2. Toggle the CS signal of all ADE9103/ADE9112/ADE9113 devi-

ces simultaneously, which can be either a null SPI command

with no SCLK toggles or part of a valid command.

3. Wait 3 cycles of DREADY for the update to take effect.

To perform an ALIGN using dedicated SPI, set PREP_BROAD-

CAST = 1 during Step 1. When an ALIGN is performed, all phases

present ADC output distortions. It is recommended that this com-

mand be executed at power-up or after a hardware or software

reset to minimize impact on accuracy.

To only verify the counters of all devices using a daisy-chain SPI

configuration, take the following steps:

1. Write to SYNC_SNAP of all ADE9103/ADE9112/ADE9113 devi-

ces to prepare for an ALIGN. Set PREP_BROADCAST = 0,

ALIGN = 0, and SNAPSHOT = 1

2. Toggle the CS signal of all ADE9103/ADE9112/ADE9113 devi-

ces simultaneously, which can be either a null SPI command

with no SCLK toggles or part of a valid command.

3. Read back the ADC synchronization counter via the SNAP-

SHOT_COUNT_HI and SNAPSHOT_COUNT_LO registers.

4. Compare values from each ADE9103/ADE9112/ADE9113 coun-

ter and ensure these values are within ±1 count difference

between them.

If an ALIGN broadcast is performed while actively sampling instead

of during the start-up procedure, it results in a discontinuity in the

waveform samples impacting up to three samples. This discontinui-

ty can result in up to a 0.1% error at half of the full-scale inputs

during a RMS calculation. Synchronization typically only has to be

performed at power up unless the SNAPSHOT_COUNT_HI and

SNAPSHOT_COUNT_LO registers show more than a ±1 count

difference. It is not recommended to continuously synchronize in a

short period of time.

Figure 55. Counter Value Communicated Using Two 8-Bit Registers

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