ADE9113 datasheet(38/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

APPLICATIONS INFORMATION

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Rev. A | 38 of 55

SPI Long Format Operation

Every long format operation consists of a 128-bit response on

the MISO data line. Every transaction regardless of read or write

includes the command response, STATUS0, STATUS1, I_WAV,

V1_WAV, V2_WAV, and CRC_CCITT. The remaining bits are de-

pendent on whether the previous command was a read or a write.

See Table 13 for details. Long format SPI transactions are required

when using the daisy-chain SPI configuration.

The read operation using the ADE9103/ADE9112/ADE9113 SPI is

initiated when the main sets the CS pin low and begins outputting

the SCLK signal. The main transmits the command packet on the

last 32 clock cycles of the transaction. The bit composition of the

command packet is shown in Table 13. Bit 31 (R/W) determines the

type of operation. For a read, R/W must be set to 1. For a write,

R/W must be cleared to 0. Bit 30 (LONG) determines the size of

the response on the next operation. For a long format response,

LONG must be set to 1. For a short format response, LONG must

be cleared to 0. Bits[29:24] are unused and must be set to 0x00.

Bits[23:16] (ADDR) represent the address of the register to be read

or written. The ADE9103/ADE9112/ADE9113 SPI samples data on

the low to high transitions of SCLK. During this operation, the

MISO line contains the response to the previous command packet.

After the main device completes 128 SCLK cycles, it sets the

CS and SCLK lines high, and the communication ends. The data

lines, MOSI and MISO, go into a high impedance state. During the

following transaction, the ADE9103/ADE9112/ADE9113 line outputs

its 128-bit read response on MISO. This operation contains the data

read in ADDR as well as ADDR + 1. Figure 49 shows a long format

read operation followed by the response.

The write operation using the ADE9103/ADE9112/ADE9113 SPI is

initiated when the main sets the CS pin low and begins outputting

the SCLK signal. The main transmits the command packet on the

last 32 clock cycles of the transaction. R/W must be cleared to

0. LONG must be set to 1. ADDR represents the address of the

ten into the address in ADDR. The ADE9103/ADE9112/ADE9113

SPI samples data on the low to high transitions of SCLK. During

this operation, the MISO line contains the response to the previous

command packet. After the main device completes 128 SCLK

cycles, it sets the CS and SCLK lines high, and the communication

ends. The data lines, MOSI and MISO, go into a high impedance

state, and the write completes with a single operation. During the

following transaction, the ADE9103/ADE9112/ADE9113 line outputs

its 128-bit write response on MISO. This response includes a read

back of the address written to on the previous operation. See

Figure 50 for details of the SPI write operation.

Table 13. Command Byte for SPI Read/Write Operations

Bit Field

Location

Bit Field

Name

Description

R/W

Set this bit to 1 if an SPI read operation is

executed.

Clear this bit to 0 if an SPI write operation is

executed.

LONG

Set this bit to 1 for a long frame structure.

Set this bit to 0 for a short frame structure.

[29:24]

RSRVD

Program to 0x00.

[23:16]

ADDR

Address of the register to be read or written.

[15:8]

DATA

Data payload if a write operation is executed.

[7:0]

CRC

CRC calculation over Bits[31:8].

Figure 49. Long Format Read SPI Transaction

Figure 50. Long Format Write SPI Transaction

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