ADE9113 datasheet(45/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

POWER MANAGEMENT

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Rev. A | 45 of 55

When EMI_LO_MASK = EMI_HI_MASK, the frequency masking

is disabled. As shown in Figure 57, a smaller value in the

EMI_LO_MASK or EMI_HI_MASK corresponds to a higher frequen-

cy and a larger value corresponds to a lower frequency. When a

new value is written into EMI_LO_MASK or EMI_HI_MASK, the

ongoing ramp is not interrupted. The new value is loaded when

the sawtooth reverts to the minimum or maximum or when the

ramp changes directions. To prevent any errors, avoid the following

scenarios:

1. The value written to EMI_LO_MASK being less than

EMI_HI_MASK.

2. EMI_LO_MASK is equal to EMI_LO_LIMIT, and EMI_HI_MASK

is equal to EMI_HI_LIMIT.

During these scenarios, the emissions are no longer a spread

spectrum but a single tone at 360 MHz, which leads to stronger

emissions that are more difficult to manage in the PCB layout.

Figure 57. Available Frequency Range with Masking Enabled

Table 18. Address 0x009, EMI_CONFIG, Bits[2:0], Electromagnetic

Interference (EMI) Frequency Hopping Selection

Bits[2:0]

Mode

Description

000

Sawtooth

frequency

rising

The frequency starts at the low limit, ramps up

to the high limit, and then returns to the low

limit.

001

Sawtooth

frequency

falling

Frequency starts at the high limit, ramps down

to the low limit, and then returns to the high

limit.

010

Ramp

Frequency ramps up and down between the

low and high limit.

011

Random

hopping

frequency

(default)

Frequency randomly hops around the

360 MHz center frequency, which is the

recommended mode.

SOFTWARE RESET

The SWRST register (Address 0x001) manages the software reset

functionality. The default value of this register is 0x00. If this register

is set to 0xD6, the ADE9103/ADE9112/ADE9113 enter the software

reset state. In this state, all the internal registers are reset to

their default values. The DC-to-DC converter continues to function.

When the software reset ends, the SWRST register clears automat-

ically to 0, and Bit 5 (RESET_DONE) in the STATUS0 register is set

to 1. If the configuration registers are protected using a WR_LOCK

= 0xD4 register write, first unlock the registers by writing WR_LOCK

= 0x5E and then write 0xD6 to the SWRST register to start a

software reset. At this point, one of the procedures described in the

Power-Up and Initialization Procedures section must be followed to

initialize the ADE9103/ADE9112/ADE9113.

HARDWARE RESET

The ADE9103/ADE9112/ADE9113 have a dedicated reset pin (RE-

SET). Hardware reset occurs when the RESET pin is brought low

(default state is a weak pullup) for at least 1.5 μs.

During a hardware reset, all the registers are set to their default

values, and the DC-to-DC converter and LDO regulators are shut

down. This procedure can be done simultaneously for all ADE9103/

ADE9112/ADE9113 devices in a polyphase energy meter. At the

end of the reset period, the ADE9103/ADE9112/ADE9113 sets Bit 5

(RESET_DONE) to 1 in the STATUS0 register. At this point, one of

the procedures described in the Power-Up and Initialization Proce-

dures section must be followed to initialize the ADE9103/ADE9112/

ADE9113 devices correctly.

POWER-DOWN MODE

There are situations in which the ADCs of the ADE9112 and

ADE9113 are not required to function, and it is desirable to lower

the current consumption of the device. Holding the RESET pin low

forces low power mode. In low power mode, the VLDOOUT, crystal

oscillator, and isolated power delivery are disabled.

RESET low on the ADE9103 sets only the digital block, SPI port,

and the clocking to low power mode. However, the analog circuit

blocks remain powered.

In systems with more than one ADE9103/ADE9112/ADE9113, the

RESET pins are tied together to lower the total current of all the

ADE9103/ADE9112/ADE9113.

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