PIC16F1507-ESLASHSS. datasheet(135/278 Pages) MICROCHIP

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DS40001586D-page 135

PIC16(L)F1507

17.1

Timer1 Operation

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 17-1 displays the Timer1 enable

selections.

17.2

Clock Source Selection

The TMR1CS<1:0> bits of the T1CON register are used

to select the clock source for Timer1. Table 17-2

displays the clock source selections.

17.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the

Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB

error in resolution will occur when reading the Timer1

value. To utilize the full resolution of Timer1, an

asynchronous input signal must be used to gate the

Timer1 clock input.

The following asynchronous sources may be used:

• Asynchronous event on the T1G pin to Timer1

gate

• C1 or C2 comparator input to Timer1 gate

17.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI. The

external clock source can be synchronized to the

microcontroller

system

clock

can

run

asynchronously.

TABLE 17-1:

TIMER1 ENABLE

SELECTIONS

TMR1ON

TMR1GE

Timer1

Operation

Off

Always On

Count Enabled

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

TABLE 17-2:

CLOCK SOURCE SELECTIONS

TMR1CS<1:0>

Clock Source

LFINTOSC

External Clocking on T1CKI Pin

System Clock (FOSC)

Instruction Clock (FOSC/4)

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