PIC16F1507-ESLASHSS. datasheet(156/278 Pages) MICROCHIP

156 / 278 page

PIC16(L)F1507

DS40001586D-page 156

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20.1.2

DATA GATING

Outputs from the input multiplexers are directed to the

desired logic function input through the data gating

stage. Each data gate can direct any combination of the

four selected inputs.

The gate stage is more than just signal direction. The

gate can be configured to direct each input signal as

inverted or non-inverted data. Directed signals are

ANDed together in each gate. The output of each gate

can be inverted before going on to the logic function

stage.

The

gating

essence

1-to-4

input

AND/NAND/OR/NOR gate. When every input is

inverted and the output is inverted, the gate is an OR of

all enabled data inputs. When the inputs and output are

not inverted, the gate is an AND or all enabled inputs.

Table 20-2 summarizes the basic logic that can be

obtained in gate 1 by using the gate logic select bits.

The table shows the logic of four input variables, but

each gate can be configured to use less than four. If

no inputs are selected, the output will be zero or one,

depending on the gate output polarity bit.

It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,

the gate output is zero, regardless of the other inputs,

but may emit logic glitches (transient-induced pulses).

If the output of the channel must be zero or one, the

recommended method is to set all gate bits to zero and

use the gate polarity bit to set the desired level.

Data gating is configured with the logic gate select

registers as follows:

• Gate 1: CLCxGLS0 (Register 20-5)

• Gate 2: CLCxGLS1 (Register 20-6)

• Gate 3: CLCxGLS2 (Register 20-7)

• Gate 4: CLCxGLS3 (Register 20-8)

numbers because other variations of this module have

multiple gate selections in the same register.

Data gating is indicated in the right side of Figure 20-2.

Only one gate is shown in detail. The remaining three

gates are configured identically with the exception that

the data enables correspond to the enables for that

gate.

20.1.3

LOGIC FUNCTION

There are eight available logic functions including:

• AND-OR

•OR-XOR

•AND

• S-R Latch

• D Flip-Flop with Set and Reset

• D Flip-Flop with Reset

• J-K Flip-Flop with Reset

• Transparent Latch with Set and Reset

Logic functions are shown in Figure 20-3. Each logic

function has four inputs and one output. The four inputs

are the four data gate outputs of the previous stage.

The output is fed to the inversion stage and from there

to other peripherals, an output pin, and back to the

CLCx itself.

20.1.4

OUTPUT POLARITY

The last stage in the configurable logic cell is the output

polarity. Setting the LCxPOL bit of the CLCxCON reg-

ister inverts the output signal from the logic stage.

Changing the polarity while the interrupts are enabled

will cause an interrupt for the resulting output transition.

Note:

Data gating is undefined at power-up.

TABLE 20-2:

DATA GATING LOGIC

CLCxGLS0

LCxG1POL

Gate Logic

0x55

AND

0x55

NAND

0xAA

NOR

0xAA

0x00

Logic 0

0x00

Logic 1

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