PIC16F1507-ESLASHSS. datasheet(157/278 Pages) MICROCHIP

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DS40001586D-page 157

PIC16(L)F1507

20.1.5

CLCx SETUP STEPS

The following steps should be followed when setting up

the CLCx:

• Disable CLCx by clearing the LCxEN bit.

• Select desired inputs using CLCxSEL0 and

CLCxSEL1 registers (See Table 20-3).

• Clear any associated ANSEL bits.

• Set all TRIS bits associated with inputs.

• Clear all TRIS bits associated with outputs.

• Enable the chosen inputs through the four gates

using CLCxGLS0, CLCxGLS1, CLCxGLS2, and

CLCxGLS3 registers.

• Select the gate output polarities with the

LCxPOLy bits of the CLCxPOL register.

• Select the desired logic function with the

LCxMODE<2:0> bits of the CLCxCON register.

• Select the desired polarity of the logic output with

the LCxPOL bit of the CLCxPOL register. (This

step may be combined with the previous gate

output polarity step).

• If driving a device, set the LCxOE bit in the

CLCxCON register and also clear the TRIS bit

corresponding to that output.

• If interrupts are desired, configure the following

bits:

- Set the LCxINTP bit in the CLCxCON register

for rising event.

- Set the LCxINTN bit in the CLCxCON

- Set the CLCxIE bit of the associated PIE

registers.

- Set the GIE and PEIE bits of the INTCON

• Enable the CLCx by setting the LCxEN bit of the

CLCxCON register.

20.2

CLCx Interrupts

An interrupt will be generated upon a change in the

output value of the CLCx when the appropriate interrupt

enables are set. A rising edge detector and a falling

edge detector are present in each CLC for this purpose.

The CLCxIF bit of the associated PIR registers will be

set when either edge detector is triggered and its asso-

ciated enable bit is set. The LCxINTP enables rising

edge interrupts and the LCxINTN bit enables falling

edge interrupts. Both are located in the CLCxCON

To fully enable the interrupt, set the following bits:

• LCxON bit of the CLCxCON register

• CLCxIE bit of the associated PIE registers

• LCxINTP bit of the CLCxCON register (for a rising

edge detection)

• LCxINTN bit of the CLCxCON register (for a

falling edge detection)

• PEIE and GIE bits of the INTCON register

The CLCxIF bit of the associated PIR registers, must

be cleared in software as part of the interrupt service. If

another edge is detected while this flag is being

cleared, the flag will still be set at the end of the

sequence.

20.3

Output Mirror Copies

Mirror copies of all LCxCON output bits are contained

in the CLCxDATA register. Reading this register reads

the outputs of all CLCs simultaneously. This prevents

any reading skew introduced by testing or reading the

CLCxOUT bits in the individual CLCxCON registers.

20.4

Effects of a Reset

The CLCxCON register is cleared to zero as the result

of a Reset. All other selection and gating values remain

unchanged.

20.5

Operation During Sleep

The CLC module operates independently from the

system clock and will continue to run during Sleep,

provided that the input sources selected remain active.

The HFINTOSC remains active during Sleep when the

CLC module is enabled and the HFINTOSC is

selected as an input source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and as a CLC input

source, when the CLC is enabled, the CPU will go idle

during Sleep, but the CLC will continue to operate and

the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

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