STA382BWSTR datasheet(154/172 Pages) STMICROELECTRONICS

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STA382BWS

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Doc ID 022784 Rev 1

Figure 43.

Alternate function for INTLINE pin

7.22.5

Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,

D3, D2)

As per Section 7.22.2, the assertion of PWDN activates a counter that, by default, after 13

million clock cycles puts the power bridge in tristate mode, independently from the fade-out

time. Using these registers it is possible to program this counter according to the following

table.

Table 173.

PNDLSL bits configuration

7.22.6

Short-circuit check enable bit (address 0x4C, bit D0)

This bit, when enabled, will activate the short-circuit checks before any power bridge

activation (EAPD bit 0->1). See section 7.20 for more details.

‘0 ’

LPD

“is th e device in powerdown?”

LP D P

LPD E

Po w er B rid ge Fau lt

IN T L IN E

PNDLSL[2]

PNDLSL[1]

PNDLSL[2]

Fade-out time

Default time (13M PLL clock cycles)

Default time divided by 2

Default time divided by 4

Default time divided by 8

Default time divided by 16

Default time divided by 32

Default time divided by 64

Default time divided by 128

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- Obsolete

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