STA382BWSTR datasheet(153/172 Pages) STMICROELECTRONICS

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STA382BWS

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7.22.2

Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)

A fade-out procedure is started in the STA382BWS once the PWDN function is enabled, and

after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down

(tristate mode). There is also the possibility to change this behavior so that the power bridge

will be switched off immediately after the PWDN pin is tied to ground, without waiting for the

13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the

immediate power-down will generate a pop noise at the output, therefore this procedure

must be used only in case pop noise is not relevant in the application. Note that this feature

works only for hardware PWDN assertion and not for a power-down applied through the IIC

interface. Refer to Section 7.22.5 if programming a different number of clock cycles is

needed.

7.22.3

Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)

This bit, when set, activates a mute output in case the volume reaches a value lower

than -76 dBFS.

7.22.4

External amplifier hardware pin enabler (LPDP, LPD LPDE) bits

(address 0x4C, bit D7, D6, D5)

Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register

settings, can be reconfigured as hardware pin enabler for an external headphone or line

amplifier.

In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or

1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.

The LPDP bit, when set, negates the value programmed as the LPD value, refer to the

following table.

Table 172.

External amplifier enabler configuration bits

LPDP

LPD

LPDE

Pin 42 output

INT_LINE

Obsolete

Product(s)

- Obsolete

Product(s)

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