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STA382BWSTR 数据表(PDF) 149 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 149 Page - STMicroelectronics |
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149 / 172 page  STA382BWS Register description: Sound Terminal compatibility Doc ID 022784 Rev 1 149/172 The output PLL frequency formula is: where Fin is the input clock frequency from the pad. Table 166. PLL factors PLL parameter Min Max FRAC 0 65535 IDIV 0 3 NDIV 5 55 Table 167. PLL register 0x43 bits Bit R/W RST Name Description 7R/W 0 PLL_DITH(1:0) ‘00’: PLL clock dithering disabled ‘01’: PLL clock dithering enabled (triangular)) ‘10’: PLL clock dithering enabled (rectangular) ‘11’: Reserved 6R/W 0 5R/W 0 NDIV PLL loop divider 4R/W 0 3R/W 0 2R/W 0 1R/W 0 0R/W 0 Table 168. PLL register 0x44 bits Bit R/W RST Name Description 7 R/W 0 PLL_DPD ‘0’: any PLL dividers change is implemented via PLL power-down ‘1’: PLL divider change will happen without PLL power-down 6 R/W 0 PLL_FCT ‘0’: PLL use integer ratio ‘1’: PLL use fractional ratio 5 R/W 0 PLL_STB PLL synchronous divider changes strobe 4 R/W 0 PLL_STBBYP ‘0’: PLL_STB is active ‘1’: PLL_STB control is bypassed 3R/W 0 PLL_IDIV (3:0) Input PLL divider 2R/W 0 1R/W 0 0R/W 0 Fin NDIV () IDIV 1 + () --------------------------- FRAC 65536 ----------------- ⎝⎠ ⎛⎞ + ⎝⎠ ⎛⎞ × Obsolete Product(s) - Obsolete Product(s) |
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