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STA382BWSTR 数据表(PDF) 148 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 148 Page - STMicroelectronics |
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148 / 172 page  Register description: Sound Terminal compatibility STA382BWS 148/172 Doc ID 022784 Rev 1 Two different behaviors can be configured by the VRESTG bit. If VRESTG=’0’ the CxVR contribution will be applied immediately after the corresponding I2C bits are written. If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the corresponding CxVol register or master volume register is written (even to the previous values). Table 165. Extra volume resolution enable 7.19 PLL configuration registers (address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) By default the STA382BWS is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’). VRESEN VRESTG Mode 0 0 Extra volume resolution disabled 0 1 Extra volume resolution disabled 1 0 Fine volume tuning enabled and applied immediately 11 Fine volume tuning enabled and applied when master or channel volume is updated D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC[15:8] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC[7:0] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DITH[1:0] PLL_NDIV[5:0] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DPD PLL_FCT PLL_STB PLL_STBBYP PLL_IDIV(3:0) 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved PLL_DIRP PLL_PWD PLL_BYP OSC_PD Reserved BOOST32K 00 00 01 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved BYPSTATE PDSTATE OSCOK LOWCK NA NA NA NA NA NA NA NA Obsolete Product(s) - Obsolete Product(s) |
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