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L9963E 数据表(PDF) 154 Page - STMicroelectronics |
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L9963E 数据表(HTML) 154 Page - STMicroelectronics |
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154 / 184 page  Figure 48. How to connect cell modules and busbar L9963E VBAT GNDREF CGND DGND AGND ISENSEp ISENSEm RSENSE S2 B2_1 C1 S1 C0 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD CELL1 CELL2 C14 S4 B4_3 C3 S3 C2 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD CELL3 CELL4 S6 B6_5 C5 S5 C4 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD BUSBAR CELL6 S8 B8_7 C7 S7 C6 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD CELL7 CELL8 S10 B10_9 C9 S9 C8 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD CELL9 BUSBAR S12 B12_11 C11 S11 C10 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD CELL11 CELL12 S14 B14_13 C13 S13 C12 RLPF RLPF RDIS RDIS CLPF CLPF CESD CESD CELL13 CELL14 RLPF CESD FR_BAT BATT_MINUS BATT_PLUS CISENSE_1 GND CBAT_1 CVCOM CVANA RFAULTL RBAT_DOWN RFAULT_DOWN FAULT_DOWN BAT_DOWN COPT BATT_UP CFLTH DZ_FLT RFLT_PD FAULT_UP ISOLp_UP ISOLm_UP ISOHp_DOWN ISOHm_DOWN RTERM RTERM GPIO9 RNTC RVTREF CNTC RGPIO GPIO8 RNTC RVTREF CNTC RGPIO GPIO7 RNTC RVTREF CNTC RGPIO GPIO6 RNTC RVTREF CNTC RGPIO GPIO5 RNTC RVTREF CNTC RGPIO GPIO4 RNTC RVTREF CNTC RGPIO GPIO3 RNTC RVTREF CNTC RGPIO CBOOT TRANSF TRANSF OPT DZBAT CVTREF CESD RISENSE RISENSE CESD CBAT_2 CISENSE_2 CISENSE_3 VCELL10_EN = 0 VCELL5_EN = 0 DO NOT CONNECT BUSBAR HERE VBUS VBUS IDISCHARGE 6.11 Communication architectures 6.11.1 Distributed BMS In the distributed approach, the BMS is made of a Master PCB and several Slave PCBs. • L9963E in the Slave PCBs is configured with SPIEN = 0, thus communicating on the vertical interface through isolated SPI • L9963E in the Master PCB is configured as SPI Slave and translates SPI frames into suitable pulses to be transmitted over the vertical interface L9963E Communication architectures DS13636 - Rev 12 page 154/184 |
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