ST52T430 datasheet(65/88 Pages) STMICROELECTRONICS

65 / 88 page

ST52T430/E430

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When the SCI Receiver is in IDLE status, it is

waiting for the START condition, which is obtained

with a logic level 0, consecutive to a logic level 1.

This condition is detected if a logic level 0 is

sampled after three logic levels 1 with the fixed

sampling time.

The recognition of the START bit forces the SCI

Receiver Block to enter in a data acquisition

sequence. The data acquisition sequence is

configured via Configuration Register 20 as

follows.

The 2 bits, M, of the Configuration Register 20

allows the definition of the serial mode as

illustrated in Table 11.1.

In the case that M=10,

Βιτ Τ8 is used to set the

parity check in order to perform (as indicated in

Table 11.1).

Recognition of the STOP condition allows data

received

from

the

Recovery

Buffer

transferred to the SCDR_RX buffer, adding the

eventual ninth data bit, according to the meaning

illustrated in previous Table 11.1. After this

operation, the RXF flag of the SCI Status Input

Control Unit reads data from the SCDR_RX buffer

(in read-only mode) with the LDRI instruction,

addressing Input Register 18, and provides a reset

at logic level 0 to the RXF flag.

If data of the Recovery Buffer is ready to be

transferred into the SCDR_RX buffer, but the

previous one was not read by the Core yet, an

OVERRUN Error takes place: the status flag

OVERR indicates the error condition. In this case,

the information stored in the SCDR_RX buffer is

not altered, but the one that has caused the

OVERRUN error can be overwritten by new data

deriving from the serial data line.

Recovery Buffer Block

This block is structured as a synchronized finite

state machine on the CLOCK_RX signal.

When the Recovery Buffer Block is in IDLE state it

waits for the reception of the correct 1 and 0

sequence representing START.

The recognition takes place by sampling the input

RX/PC5 at CLOCK_RX frequency, which has a

frequency that is 16 times higher than CLOCK_TX.

While the external transmitter sends a single bit,

the Recovery Buffer Block samples 16 states (from

SAMPLE1 to SAMPLE16).

The analysis of the RX/PC5 input signal is carried

out providing three samples for each bit received.

If these three samples are not equal, then the

noise error flag, NSERR, of Input Register 19 is set

to 1 and the data value received will be the one

assumed by the majority of the samples.

The procedure above allows SCI not to become

IDLE, because of a limited noise due to “an

erroneous

sampling”.

The

transmission

recognized as correct and the noise flag is set.

At the end of the reception of a bit, Recovery Buffer

Block will repeat the same step 9 times: one for the

stop acquisition (10 times in case of 9-bit data,

double stop or parity check).

At the end of data reception the Recovery Buffer

Block will supply information on eventual frame

errors by setting the FRERR flag bit of Input

Table 11.1 Configuration Register 20 Setting

Bit

Name

Value

Description

0TE

Transmission

Transmission ENABLED

1RE

Receiver DISABLED

Receiver ENABLED

8, No Parity, 1 bit stop

8, No Parity, 2 bit stop

8, Parity, 1 bit stop

9, No Parity, 1 bit stop

4T8

Parity Odd, if Parity is

selected (M

= 10);

otherwise 9th Data bit

Parity Even, if Parity is

selected (M = 10);

otherwise 9th Data bit

BRSL

000

600 baud

001

1200 baud

010

2400baud

011

4800 baud

100

9600 baud

101

19200 baud

110

38400 baud

111

Not Used

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