ST52T430 datasheet(49/88 Pages) STMICROELECTRONICS

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ST52T430/E430

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9.2 Register Description

The WDT timeout is defined by setting the value of

the REG_CONF 2. The first 4 bits of this register

are

used,

obtaining

different

delays

illustrated in Table 9.2. In Table 9.2 timeout is

expressed by using the number of WDT CLK. The

WDT CLK is derived from the clock master by a

division factor of 500. Timeout is obtained by

multiplying the WDT CLK pulse length for the

number of pulses defined by the configuration

pulse lengths for typical values of the clock master.

Table 9.3 illustrates the timeout WDT values when

the Master Clock is 5 MHz.

Table 9.2 WDT REG_CONF 2

Bit

Name

Value

Timeout Values (WDT

D(3:0)

0000

0001

625

0010

1250

0011

1875

0100

2500

0101

3125

0110

3750

0111

4375

1000

5000

1001

5625

1010

6250

1011

6875

1100

7500

1101

8125

1110

8750

1111

9375

4-7

Not Used

Reset Configuration ‘0000’

Table 9.3 Timeout Values with CLK = 5 MHz

Bit

Name

Value

Timeout Values (ms)

D (3:0)

0000

0.1

0001

62.5

0010

125

0011

187.5

0100

250

0101

312.5

0110

375

0111

437.5

1000

500

1001

562.5

1010

625

1011

687.5

1100

750

1101

812.5

1110

875

1111

937.5

4-7

Not Used

Reset Configuration ‘0000’

Table 9.4 Typical WDT CLK Pulse Length

MASTER CLK

(MHz)

WDT CLK

(KHz)

WDT CLK

PULSE

LENGTH (ms)

0.125

0.1

0.0625

0.05

0.025

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